• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.11
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• pp.2534-2539
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• 2015

Method for regulating voltage using a generator voltage regulating device (AVR) is divided in an existing analog system and a digital replacement. Typically, to adjust the voltage by using a brushless excitation system of the type to be reduced for a voltage change under all. The control method of the AVR as a PID (proportional-integral-differential) control method is widely used. However, the control scheme is to reduce the transient response of the control parameters of the controller to the control object. Therefore, if the control target should change, there is a problem, reset the parameters of the controller again. In this study, without having to reset the parameters of the controller for the parameter variations to be controlled iPID (intelligent PID) using a controller designed to obtain a generator AVR system voltage variation is small in response to full load is applied to and through simulations and experiments improved transient response.

• Journal of Navigation and Port Research
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• v.35 no.6
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• pp.501-507
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• 2011

This paper focuses on dispatching strategy for AGVs(Automated Guided Vehicle). The goal of AGV dispatching is assigning AGVs to requested job to minimizing the delay of QCs and the travel distance of AGVs. Due to the high dynamic nature of container terminal environment, the effect of dispatching is hard to predict thus it leads to frequent modification of dispatching decisions. In this situation, approaches based on a single rule are widely used due to its simplicity and small computational cost. However, these approaches have a limitation that cannot guarantee a satisfactory performance for the various performance measures. In this paper, dispatching strategy based on multicriteria heuristics is proposed. The Proposed strategy consists of multiple decision criteria. A multi-objective evolutionary algorithm is applied to optimize weights of those criteria. The result of simulation experiment shows that the proposed approach outperforms single rule-based dispatching approaches.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1371-1378
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• 2009

We propose a low-power eFuse one-time programmable (OTP) memory cell based on a logic process. The eFuse OTP memory cell uses separate transistors optimized at program and read mode, and reduces an operation current at read mode by reducing parasitic capacitances existing at both WL and BL. Asynchronous interface, separate I/O, BL SA circuit of digital sensing method are used for a low-power and small-area eFuse OTP memory IP. It is shown by a computer simulation that operation currents at a logic power supply voltage of VDD and at I/O interface power supply voltage of VIO are 349.5${\mu}$A and 3.3${\mu}$A, respectively. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18${\mu}$m generic process is 300 ${\times}$557${\mu}m^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2027-2032
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• 2016

The rapid diffusion of smart phones and the development of data storage and analysis technology have made the field of big-data a promising industry in the future. In the marketing field, big-data analysis on social data can be used for understanding the needs of consumers as an effective and efficient marketing tool. Before the age of big-data, companies had relied upon the traditional methods such as questionnaire survey and marketing test in which a small number of consumers had participated. The traditional methods have still been used. Although both of big-data analysis and traditional methods are useful to understand consumers. It is need to check whether the results from both include similar implications. In this point, this study attempts to compare the results of big-data analysis with that of questionnaire survey on some cosmetics brands methods. As the results of this study, both results of big-data analysis and questionnaire survey include similar implications.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.4
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• pp.775-780
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• 2007

Rapid Prototyping (RP) is a technology that produces prototype parts from 3D computer aided design model data without intermediate processing technology rapidly. CAD model data are created from 3D object digitizing systems but presented just as 2D data when they are printed as a hard copy or displayed on a monitor. However, Rapid Prototyping Technology fabricates 3D objects the same that CAD data because it transforms designed 3D CAD data into 2D cross sectional data, and manufactures layer by layer deposition sequentially. But most of all the small and medium scale companies which produce a toothbrush, a toy and such like provisions are in difficult situations to buy RP system because it is very expensive. In this paper, we propose a 3D control system adopting open source programs for implementing Rapid Prototyping Technology in order that RP system can be purchase at a moderate price.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.7_8
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• pp.341-351
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• 2003

For debugging effectively the shared-memory programs with nested parallelism, it is important to detect efficiently the first races which incur non-deterministic executions of the programs. Previous on-the-fly technique detects the first races in two passes, and shows inefficiencies both in execution time and memory space because the size of an access history for each shared variable depends on the maximum parallelism of program. This paper proposes a new on-the-fly technique to detect the first races in two passes, which is constant in both the number of event comparisons and the space complexity on each access to shared variable because the size of an access history for each shared variable is a small constant. This technique therefore makes on-the-fly race detection more efficient and practical for debugging shared-memory programs with nested parallelism.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.177-185
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• 2005

NAND-type flash memory is becoming increasingly popular as a large data storage for mobile computing devices. Since flash memory is an order of magnitude more expensive than magnetic disks, data compression can be effectively used in managing flash memory based storage systems. However, compressed data management in NAND-type flash memory is challenging because it supports only page-based I/Os. For example, when the size of compressed data is smaller than the page size. internal fragmentation occurs and this degrades the effectiveness of compression seriously. In this paper, we present an efficient flash compression layer (FCL) for NAND-type flash memory which stores several small compressed pages into one physical page by using a write buffer Based on prototype implementation and simulation studies, we show that the proposed scheme offers the storage of flash memory more than $140\%$ of its original size and expands the write bandwidth significantly.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.419-428
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• 2001

Advances in circuit and integration technology are continuously boosting the speed of processors. One of the main challenges presented by such developments is the effective use of powerful processors in shared memory multiprocessor system. We believe that the interconnection problem is not solved even for small scale shared memory multiprocessor, since the speed of shared buses is unlikely to keep up with the bandwidth requirements of new powerful processors. In the past few years, point-to-point unidirectional connection have emerged as a very promising interconnection technology. The single slotted ring is the simplest form point-to-point interconnection. The main limitation of the single slotted ring architecture is that latency of access increase linearly with the number of the processors in the ring. Because of this, we proposed the dual slotted ring as an alternative to single slotted ring for cache-based multiprocessor system. In this paper, we analyze the proposed dual slotted ring architecture using new snooping protocol and enforce simulation to compare it with single slotted ring.

• Journal of Power Electronics
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• v.13 no.6
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• pp.939-954
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• 2013

The Direct Torque Control (DTC) technique for Permanent Magnet Synchronous Motors (PMSM) is receiving increased attention due to its simplicity and robust dynamic response when compared with other control techniques. The classical switching table based DTC results in large flux and torque ripples in the motors. Several studies have been reported in the literature on classical DTC. However, there are only limited studies that actually discuss or evaluate the classical DTC. This paper proposes, novel switching table / DTC methods for PMSMs to reduce torque ripples. In this paper, two DTC schemes are proposed. The six sector and twelve sector methodology is considered in DTC scheme I and DTC scheme II, respectively. In both DTC schemes a simple modification is made to the classical DTC structure. The two level inverter available in the classical DTC is eliminated by replacing it with a three level Neutral Point Clamped (NPC) inverter. To further improve the performance of the proposed DTC scheme I, the available 27 voltage vectors are allowed to form different groups of voltage vectors such as Large - Zero (LZ), Medium - Zero (MZ) and Small - Zero (SZ), where as in DTC scheme II, all of the voltage vectors are considered to form a switching table. Based on these groups, a novel switching table is proposed. The proposed DTC schemes are comparatively investigated with the classical DTC and existing literatures through theory analysis and computer simulations. The superiority of the proposed DTC method is also confirmed by experimental results. It can be observed that the proposed techniques can significantly reduces the torque ripples and improves the quality of current waveform when compared with traditional and existing methods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.365-371
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• 2015

CB tree represents the binary trie by a compact binary sequence. However, retrieval time grows fast since the more keys stored in the trie, longer the binary sequences are. In addition it is inefficient for frequent key insertion/deletion. HCB tree is a hierarchical CB tree consisting of small binary tries. However it can not avoid shift operations and have to scan an additional table to refer child or parent trie. In order to improve retrieval performance and avoid shift operations when keys are inserted or deleted, we in this paper represent each separated trie by a full binary trie and then assign the unique identifier to it. Finally the theoretical evaluations show that both the proposed approach and HCB tree provides better than CB tree for key retrieval. The proposed approach shows the highest performance in case of key insertion/deletion and moreover requires only 71%~89% of storage as compared with CB tree.