• Title/Summary/Keyword: Slurry trench

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Behavior Characteristics of Cement Bentonite Impervious Walls Related to Mixing Methods and Curing Time (강화벤토나이트 차수벽체의 배합방법 및 양생일에 따른 거동 특성)

  • Hwang, Jungsoon;Kim, Seungwook;Jung, Jungi;Lee, Seungjoo;Oh, Byeungsam;Baek, Seungcheol
    • Journal of the Korean GEO-environmental Society
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    • v.17 no.12
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    • pp.45-54
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    • 2016
  • In this study, the construction method of new underground continuos impervious wall that the bentonite slurry keeps the stability of excavated trench and the mixture of cement and bentonite plays a role as a constituent of impervious wall in the trench. The merit of homogeneity of the method so called as a cement-bentonite slurry wall enables to accurately make an estimation of hydraulic conductivity of the walls compared with that by other general grouting methods and to verify their waterproof efficiency without difficulty at the design stage. The use of cement-bentonite slurry walls for the containment of groundwater flow has also proven a cost-effective impervious wall technology by employing the simple combination of construction equipments and easy and fast construction procedures. The engineering characteristics of cement-bentonite impervious wall obtained by carrying out the laboratory experiments under various conditions. This study reveals the effect of variation of constituent materials and their mixing methods (Water-Cement-Bentonite) on the engineering characteristics of a composition. Also, this study makes some recommendations on the optimum mixing ratio and mixing sequence for the best quality at the site. That is the most important factors to estimate the construction cost and design of the technique. The comparison is lastly made to evaluate the effect of ordinary Portland and blast furnace slag cement as a bonding material on the behavior of impervious walls.

Slug Test Analysis in Vertical Cutoff Walls with Consideration of Filter Cake (연직차수벽에서 필터케익을 고려한 순간 변위시험 해석방법)

  • Nguyen, The Bao;Lee, Chul-Ho;Choi, Hang-Seok
    • Proceedings of the Korean Geotechical Society Conference
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    • 2008.03a
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    • pp.220-228
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    • 2008
  • In constructing a slurry trench cutoff wall, a thin but relatively impermeable layer called filter cake can be formed on the excavation surface. The filter cake significantly influences the result of slug test analysis in the cutoff wall. This study is to examine the effect of filter cake on evaluating in situ hydraulic conductivity of the vertical cutoff wall along with slug test analyses. The numerical program Slug_3D was modified to take filter cake into account in the slug test simulation. With consideration of filter cake, the type curve method and the modified line-fitting method were used to reanalyze the case study taken from a landfill site. The previous results achieved by Choi and Daniel (2006b) without consideration of filter cake have been compared with the results in this study. The considerable difference between the two results shows the necessity of considering the filter cake in practice.

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Study on the Optimization of HSS STI-CMP Process (HSS STI-CMP 공정의 최적화에 관한 연구)

  • Jeong, So-Young;Seo, Yong-Jin;Park, Sung-Woo;Kim, Chul-Bok;Kim, Sang-Yong;Lee, Woo-Sun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.05c
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    • pp.149-153
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    • 2003
  • Chemical mechanical polishing (CMP) technology for global planarization of multi-level inter-connection structure has been widely studied for the next generation devices. CMP process has been paid attention to planarized pre-metal dielectric (PMD), inter-layer dielectric (ILD) interconnections. Expecially, shallow trench isolation (STI) used to CMP process on essential. Recently, the direct STI-CMP process without the conventional complex reverse moat etch process has established by using slurry additive with the high selectivity between $SiO_2$ and $Si_3N_4$ films for the purpose of process simplification and n-situ end point detection(EPD). However, STI-CMP process has various defects such as nitride residue, tom oxide and damage of silicon active region. To solve these problems, in this paper, we studied the planarization characteristics using a high selectivity slurry(HSS). As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of HSS STI-CMP process.

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A Study of End Point Detection Measurement for STI-CMP Applications (STI-CMP 공정 적용을 위한 연마 정지점 고찰)

  • 이경태;김상용;김창일;서용진;장의구
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.07a
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    • pp.90-93
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    • 2000
  • In this study, the rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.18um semiconductor device. To employ in STI CMP, the reverse moat process has been added thus the process became complex and the defects were seriously increased. Removal rates of each thin films in STI CMP was not equal hence the devices must to be effected, that is, the damage was occured in the device dimension in the case of excessive CMP process and the nitride film was remained on the device dimension in the case of insufficient CMP process than these defects affect the device characteristics. To resolve these problems, the development of slurry for CMP with high removal rate and high selectivity between each thin films was studied then it can be prevent the reasons of many defects by reasons of many defects by simplification of process that directly apply CMP process to STI structure without the reverse moat pattern process.

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Effects of Abrasive Size and Surfactant Concentration on the Non-Prestonian behavior of Nano-Ceria Slurry for STI CMP (STI CMP용 나노 세리아 슬러리의 Non-Prestonian 거동에서 연마 입자의 크기와 계면활성제의 농도가 미치는 영향)

  • ;Takeo Katoh
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2003.11a
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    • pp.64-64
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    • 2003
  • 고집적화된 시스템 LSI 반도체 소자 제조 공정에서 소자의 고속화 및 고성능화에 따른 배선층수의 증가와 배선 패턴 미세화에 대한 요구가 갈수록 높아져, 광역평탄화가 가능한 STI CMP(Shallow Trench Isolation Chemical-Mechanical-Polishing)공정의 중요성이 더해가고 있다. 이러한 STI CMP 공정에서 세리아 슬러리에 첨가되는 계면활성제의 농도에 따라 산화막과 질화막 사이의 연마 선택비를 제어하는 것이 필수적 과제로 등장하고 있다. 일반적인 CMP 공정에서 압력 증가에 따른 연마 제거량이 Prestonian 거동을 나타내는 반면, 연마 입자의 크기를 변화시켜 계면활성제의 농도를 달리 하였을 경우, 압력 변화에 따라 Non-Prestonian 거동이 나타나는 것을 고찰할 수 있었다. 따라서 본 연구에서는 세리아 슬러리 내에 첨가되는 계면활성 제의 농도와 연마입자의 크기를 달리한 후, 압력을 변화시킴으로 나타나는 non-Prestonian 거동에 미치는 영향에 대하여 연구하였다.

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Dependency of Planarization Efficiency on Crystal Characteristic of Abrasives in Nano Ceria Slurry for Shallow Trench Isolation Chemical Mechanical Polishing (STI CMP용 나노 세리아 슬러리에서 연마입자의 결정특성에 따른 평탄화 효율의 의존성)

  • Kang, Hyun-Goo;Takeo Katoh;Kim, Sung-Jun;Ungyu Paik;Park, Jea-Gun
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2003.11a
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    • pp.65-65
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    • 2003
  • Chemical mechanical polishing (CMP) is one of the most important processes in recent ULSI (Ultra Large Scale Integrated Circuit) manufacturing technology. Recently, ceria slurries with surfactant have recently been used in STI-CMP,[1] became they have high oxide-to-nitride removal selectivity and widen the processing margin The role of the abrasives, however, on the effect of planarization on STI-CMP is not yet clear. In this study, we investigated how the crystal characteristic affects the planarization efficiency of wafer surface with controlling crystallite size and poly crystalline abrasive size independently.

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Property variation of transistor in Gate Etch Process versus topology of STI CMP (STI CMP후 Topology에 따른 Gate Etch, Transistor 특성 변화)

  • Kim, Sang-Yong;Chung, Hun-Sang;Park, Min-Woo;Kim, Chang-Il;Chang, Eui-Goo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.11b
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    • pp.181-184
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    • 2001
  • Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

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Property variation of transistor in Gate Etch Process versus topology of STI CMP (STI CMP후 Topology에 따른 Gate Etch, Transistor 특성 변화)

  • 김상용;정헌상;박민우;김창일;장의구
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.11a
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    • pp.181-184
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    • 2001
  • Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

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