• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4C
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• pp.185-190
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• 2005

In IS-95 and IMT-2000 systems using variable code rates and constraint lengths, this paper limits code rate 1/2 and constraint length 3 and realizes forward real-time decoder using Sliding-Window with decoding length 6 and PVSL(Prototype Vector Selecting Logic), LVQ(Learning Vector Quantization) in Neural Network. In comparison condition to theoretically constrained AWGN channel environment at $S/(N_{0}/2)=1$ I verified the superiority of forward real-time decoder through hard-decision and soft-decision comparison between Viterbi decoder and forward real-time decoder such as BER and Secure Communication and H/W Structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12A
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• pp.1387-1395
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• 2004

Turbo decoder inherently requires large memory and intensive hardware complexity due to iterative decoding, despite of excellent decoding efficiency. To decrease the memory space and reduce hardware complexity, various design issues have to be discussed. In this paper, various design issues on Turbo decoder are investigated and the tradeoffs between the hardware complexity and the performance are analyzed. Through the various simulations on the fixed-length analysis, we decided 5-bits for the received data, 6-bits for a priori information, and 7-bits for the quantization state metric, so the performance gets close to that of infinite precision. The MAX operation which is the main function of Log-MAP decoding algorithm is analyzed and the error correction term for MAX* operation can be efficiently implemented with very small hardware overhead. The size of the sliding window was decided as 32 to reduce the state metric memory space and to achieve an acceptable BER.