• Journal of Biomedical Engineering Research
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• v.25 no.2
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• pp.137-144
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• 2004

ECG signals are often contaminated with high-frequency noise such as muscle artifact, power line interference, and others. In the ECG signal processing, especially during a pre-processing stage, numerous noise removal techniques have been used to reduce these high-frequency noise without much distorting the original signal. This paper proposes a new type of digital filter with a continuously variable cutoff frequency to improve the signal quality This filter consists of a cutoff frequency controller (CFC) and variable cutoff frequency lowpass filter (VCF-LPF). From the noisy input ECG signal, CFC produces a cutoff frequency control signal using the signal slew rate. We implemented VCF-LPF based on two new filter design methods called convex combination filter (CCF) and weight interpolation fille. (WIF). These two methods allow us to change the cutoff frequency of a lowpass filter In an arbitrary fine step. VCF-LPF shows an excellent noise reduction capability for the entire time segment of ECG excluding the rising and falling edge of a very sharp QRS complex. We found VCF-LPF very useful and practical for better signal visualization and probably for better ECG interpretation. We expect this new digital filter will find its applications especially in a home health management system where the measured ECG signals are easily contaminated with high-frequency noises .

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.9
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• pp.6247-6253
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• 2015

This paper presents the transient-response improved LDO regulator based on parallel error amplifiers. The proposed LDO regulator consists of an error amplifier (E/A1) which has a high gain and narrow bandwidth and a second amplifier (E/A2) which has low gain and wide bandwidth. These amplifiers are in parallel structure. Also, to improve the transient-response properties and slew-rate, some circuit block is added. Using pole-splitting technique, an external capacitor is reduced in a small on-chip size which is suitable for mobile devices. The proposed LDO has been designed and simulated using a Megna/Hynix $0.18{\mu}m$ CMOS parameters. Chip layout size is $500{\mu}m{\times}150{\mu}m$. Simulation results show 2.5 V output voltage and 100 mA load current in an input condition of 2.7 V ~ 3.3 V. Regulation Characteristic presents voltage variation of 26.1 mV and settling time of 510 ns from 100mA to 0 mA. Also, the proposed circuit has been shown voltage variation of 42.8 mV and settling time of 408 ns from 0 mA to 100 mA.