• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2576-2578
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• 2001

Elliptic curve cryptosystems based on discrete logarithm problem in the group of points of an elliptic curve defined over a finite field. The discrete logarithm in an elliptic curve group appears to be more difficult than discrete logarithm problem in other groups while using the relatively small key size. An implementation of elliptic curve cryptosystems needs finite field arithmetic computation. Hence finite field arithmetic modules must require less hardware resources to archive high performance computation. In this paper, a new architecture of finite field multiplier using conversion scheme of normal basis representation into polynomial basis representation is discussed. Proposed architecture provides less resources and lower complexity than conventional bit serial multiplier using normal basis representation. This architecture has synthesized using synopsys FPGA express successfully.

• Journal of Electrical Engineering and Technology
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• v.13 no.4
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• pp.1549-1557
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• 2018

Optimizing the design of large-scale electric machines based on nonlinear finite element analysis (FEA) requires longer computation time than other applications of FEA, mainly due to the huge size of the machines. This paper addresses a new region decision method (RDM) with mesh adaptive direct search (MADS) for the optimal design of wind generators in order to reduce the computation time. The validity of the proposed algorithm is evaluated using Rastrigin and Goldstein-Price benchmark function. Moreover, the algorithm is employed for the optimal design of a 5.6MW interior permanent magnet synchronous generator to minimize the torque ripple. Additionally, mechanical stress analysis as well as electromagnetic field analysis have been implemented to prevent breakdown caused by large centrifugal forces of the modified design.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.291-297
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• 2006

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 128-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array. This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We designed the circuits with goals of the high-speed computations and the simplified structures.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.321-325
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• 2006

Because strong wind is one of the few forces that, although considered in container crane design, still cause significant damage, a container crane was tested to investigate wind load characteristic in uniform flows. So, this study measured an external point pressure at the each members of a container crane according to a wind direction and a shape of members in a wind-tunnel test. The result of this test was compared to those of computation fluid dynamics using a CFX 10. The scale of a container crane model for wind tunnel test applied similarity scales to consider the size of the wind tunnel test section and the boundary condition for CFD is like wind tunnel test.

• Structural Engineering and Mechanics
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• v.11 no.1
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• pp.17-34
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• 2001

An improved method has been developed for the computation of the section forces and stiffness in nonlinear finite element analysis of RC plane frames. The need for a new approach arises because the conventional technique may have a questionable level of efficiency if a large number of layers is specified and a questionable level of accuracy if a smaller number is used. The proposed technique is based on automatically dividing the section into zones of similar state of stress and tangent modulus and then numerically integrating within each zone to evaluate the sectional stiffness parameters and forces. In the new system, the size, number and location of the layers vary with the state of the strains in the cross section. The proposed method shows a significant improvement in time requirement and accuracy in comparison with the conventional layered approach. The computer program based on the new technique has been used successfully to predict the experimental load-deflection response of a RC frame and good agreement with test and other numerical results have been obtained.

• Journal of Institute of Convergence Technology
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• v.8 no.1
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• pp.15-20
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• 2018

Recently a GPU has acquired programmability to perform general purpose computation fast by running thousands of threads concurrently. This paper presents a parallel GPU computation algorithm for dense matrix-matrix addition and scalar multiplication using OpenGL compute shader. It can play a very important role as a fundamental building block for many high-performance computing applications. Experimental results on NVIDIA Quad 4000 show that the proposed algorithm runs 21 times faster than CPU algorithm and achieves performance of 16 GFLOPS in single precision for dense matrices with size 4,096. Such performance proves that our algorithm is practical for real applications.

• Journal of Multimedia Information System
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• v.6 no.1
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• pp.7-14
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• 2019

This work presents a virtual prototyping design approach for an area-based image stitching hardware. The virtual hardware obtained from virtual prototyping is equivalent to the conceptual algorithm, yet the conceptual blocks are linked to the actual circuit components including the memory, logic gates, and arithmetic units. Through the proposed method, the overall structure, size, and computation speed of the actual hardware can be estimated in the early design stage. As a result, the optimized virtual hardware facilitates the hardware implementation by eliminating trail design and redundant simulation steps to optimize the hardware performance. In order to verify the feasibility of the proposed method, the virtual hardware of an image stitching platform has been realized, where it required 10,522,368 clock cycles to stitch two $1280{\times}1024$ sized images. Furthermore, with a clock frequency of 250MHz, the estimated computation time of the proposed virtual hardware is 0.877sec, which is 10x faster than the software-based image stitch platform using MATLAB.

• The Journal of Korea Robotics Society
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• v.17 no.1
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• pp.16-24
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• 2022

This paper presents a method that can reduce the computational cost of the hierarchical quadratic programming (HQP)-based robot controller. Hierarchical controllers can effectively manage articulated robots with many degrees of freedom (DoFs) to perform multiple tasks. The HQP-based controller is one of the generic hierarchical controllers that can provide a control solution guaranteeing strict task priority while handling numerous equality and inequality constraints. However, according to a large amount of computation, it can be a burden to use it for real-time control. Therefore, for practical use of the HQP, we propose a method to reduce the computational cost by decreasing the size of the decision variable. The computation time and control performance of the proposed method are evaluated by real robot experiments with a 15 DoFs dual-arm manipulator.

• International journal of advanced smart convergence
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• v.12 no.2
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• pp.117-126
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• 2023

To improve the overall performance and realism of your game, it is important to calculate the trajectory of a projectile accurately and quickly. One way to increase realism is to use a ballistic model that takes into account factors such as air resistance, density, and wind when calculating a projectile's trajectory. However, the more these factors are taken into account, the more computationally time-consuming and expensive it becomes, creating a trade-off between overall performance and efficiency. Therefore, we present an optimal solution to find a balance between ballistic model accuracy and computation time. We perform ballistic calculations using numerical methods such as Euler, Velocity Verlet, RK2, RK4, and Akima interpolation, and measure and compare the computation time, memory usage (RSS, Resident Set Size), and accuracy of each method. We show developers how to implement more accurate and efficient ballistic models and help them choose the right computational method for their numerical applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.159-161
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• 2017

In this paper, we propose an adaptive search range allocation algorithm for high-performance HEVC encoder and a hardware architecture suitable for the proposed algorithm. In order to improve the prediction performance, the existing motion vector is configured with the motion vectors of the neighboring blocks as prediction vector candidates, and a search range of a predetermined size is allocated using one motion vector having a minimum difference from the current motion vector. The proposed algorithm reduces the computation time by reducing the size of the search range by assigning the size of the search range to the rectangle and octagon type according to the structure of the motion vectors for the surrounding four blocks. Moreover, by using all four motion vectors, it is possible to predict more precisely. By realizing it in a form suitable for hardware, hardware area and computation time are effectively reduced.