• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.479-479
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• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• 마이크로전자및패키징학회지
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• 제24권4호
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• pp.91-95
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• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.39.2-39.2
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• 2011

With the steady increase in the demand for flexible devices, mainly in display panels, researchers have focused on finding a novel material that have excellent electrical properties even when it is bended or stretched, along with superior mechanical and thermal properties. Graphene, a single-layered two-dimensional carbon lattice, has recently attracted tremendous research interest in this respect. However, the limitations in the growing method of graphene, mainly chemical vapor deposition on transition metal catalysts, has posed severe problems in terms of device integration, due to the laborious transfer process that may damage and contaminate the graphene layer. In addition, to lower the overall cost, a fabrication technique that supports low temperature and low vacuum is required, which is the main reason why solution-based process for graphene layer deposition has become the hot issue. Nonetheless, a direct deposition method of large area, few-layered, and uniform graphene layers has not been reported yet, along with a convenient method of patterning them. Here, we report an evaporation-induced technique for directly depositing few layers of graphene nanosheets with excellent uniformity and thickness controllability on any substrate. The printed graphene nanosheets can be patterned into desired shapes and structures, which can be directly applicable as flexible and transparent electrode. To illustrate such potential, the transport properties and resistivity of the deposited graphene layers have been investigated according to their thickness. The induced internal flow of the graphene solution during tis evaporation allows uniform deposition with which its thickness, and thus resistivity can be tuned by controlling the composition ratio of the solute and solvent.

• 대한전자공학회논문지SD
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• 제41권10호
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• pp.51-56
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• 2004

광소자의 재료물질로서 특성이 우수하며 열광학계수가 큰 silicon을 기반으로 한 SOI (Silicon-on-insulator)를 사용하여 열광학 1×2 광스위치를 제안, 제작하였다. SOI wafer는 도파로가 형성될 상위 Si 층(n=3.5)과 클래딩 영역이 될 산화막 매립층(n=1.5) 그리고 기판인 Si인 3층으로 이루어진다. BPM(Beam propagation method) 전산모의를 통해 20dB 이상의 누화특성을 갖는 단일모드의 1×2 비대칭 y-분기 광도파로를 형성하고, 열확산 전산모의를 통해 금속열선을 설계 제작하였다. 제작된 광스위치는 약 3.5 watts의 구동 전력에서 20dB 이상의 채널간 누화가 측정되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권3호
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• pp.166-176
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• 2007

Radio frequency (RF) microelectromechanical systems (MEMS) have been pursued for more than a decade as a solution of high-performance on-chip fixed, tunable and reconfigurable circuits. This paper reviews our research work on RF MEMS switches and switching circuits in the past five years. The research work first concentrates on the development of lateral DC-contact switches and capacitive shunt switches. Low insertion loss, high isolation and wide frequency band have been achieved for the two types of switches; then the switches have been integrated with transmission lines to achieve different switching circuits, such as single-pole-multi-throw (SPMT) switching circuits, tunable band-pass filter, tunable band-stop filter and reconfigurable filter circuits. Substrate transfer process and surface planarization process are used to fabricate the above mentioned devices and circuits. The advantages of these two fabrication processes provide great flexibility in developing different types of RF MEMS switches and circuits. The ultimate target is to produce more powerful and sophisticated wireless appliances operating in handsets, base stations, and satellites with low power consumption and cost.

• 한국표면공학회지
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• 제47권6호
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• pp.297-302
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• 2014

ZnS nanowires were synthesized in order to investigate $NO_2$ gas sensing properties. They were grown on the sapphire substrate using ZnS powders. SEM (scanning electron microscopy) showed the diameter and length of the ZnS nanowires were approximately in the range of 50 - 100 nm and a few $10s\;{\mu}m$, respectively. They were also found to be composed of Wurtzite- structured single crystals from TEM (transmission electron microscopy) analysis. $NO_2$ gas sensing performance of the ZnS nanowire was measured with electrical resistance changes caused by $NO_2$ gas with a concentration of 1-5ppm. The sensor was UV treated with an intensity of $1.2mW/cm^2$ to facilitate charge carrier transfer. The responses of the ZnS nanowires to the $NO_2$ gas at room temperature, treated with UV of two different wavelengths of 365 nm and 254 nm, are measured to be 124.53 - 206.87 % and 233.97 - 554.83%, respectively. In the current work, the effect of UV treatment on the gas sensing performance of the ZnS nanowires was studied. And the underlying mechanism for the electrical resistance changes of the ZnS nanowires by $NO_2$ gas was also discussed.

• 대한기계학회논문집B
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• 제39권7호
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• pp.567-578
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• 2015

Leidenfrost 온도 이상으로 가열된 벽면과 충돌하는 액적의 속도가 열전달 특성에 미치는 영향에 관한 실험 연구를 수행하였다. 동기화된 초고속 가시화 카메라와 적외선 카메라를 이용하여 벽면과 충돌하는 액적의 충돌 특성과 충돌면의 온도 분포를 측정하였다. 획득한 표면온도 분포를 충돌면의 경계 조건으로 이용하여 가열 벽면의 3차원 비정상 열전도 수치해석을 통해 표면 열유속 분포를 얻었다. 수직방향 충돌속도가 증가할수록 최대 액막 직경이 증가하고 가열 벽면과 액막 사이에 존재하는 증기막의 두께가 감소하여 열전달 효율이 증가하였다. 액적은 웨버수가 30보다 작은 경우 되튐현상이 발생하였으며, 큰 경우 작은 액적들로 분쇄되어졌다. 충돌속도에 의한 열전달량의 증가 경향이 되튐영역에서 분쇄영역에서 가면서 약화되었으며, 이는 분쇄현상에 의해 유효 열전달 면적의 확대 효과가 저감되었기 때문으로 해석된다.

• 한국진공학회지
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• 제7권4호
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• pp.328-333
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• 1998

저압 유기금속 화학증착법을 이용하여 (001) InP 기판 위에 격자 일치된 InAlAs 에 피층 성장 결과 620~$700^{\circ}C$범위에서 성장 온도가 증가할수록 산소 유입량의 감소 때문으로 생각되는 광학적 성질의 향상이 관찰되었으나 $750^{\circ}C$이상의 고온에서는 InP완충층의 열화에 의한 결정성의 감소가 발견되었다. 또한, AsH3의 유량이 증가됨에 따라 성장된 InAlAs층의 Al함유량이 증가하는 현상이 관찰되었고, 이는 Al-As와 In-As의 bond strength 차이로 설 명하였다. InGaAs/InAlAs 단일 양자우물구조에서 측정된 우물두께에 따른 photoluminescence peak energy는 계산 값과 잘 일치하였고, high resolution x-ray diffraction 측정을 통하여 뚜렷한 satellite peak와 fine thickness fringe들이 관찰되는 우수 한 계면특성을 가지는 다중 양자우물구조가 성장됨을 확인하였다.

• Korean Chemical Engineering Research
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• 제58권3호
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• pp.369-380
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• 2020

대부분의 단결정 실리콘 잉곳은 초크랄스키(Czochralski(Cz)) 공정으로 제조된다. 그러나 단결정 실리콘 잉곳을 제품화 및 태양 전지 기판으로 가공하였을 때 산소 불순물이 있는 경우 낮은 효율성을 나타내는 경향이 있다. 단결정 Si-잉곳의 생산을 위해서는 용융 Si를 녹인 다음 단결정 Si의 시드(Seed)로 결정화하는 초크랄스키(Cz) 공정을 도입한다. 용융된 다결정 Si-덩어리를 단결정 Si-잉곳으로 결정성장 될 때, 열 전달은 Cz-공정의 구조에서 중요한 역할을 한다. 본 연구에서 고품질 단결정 실리콘 잉곳을 얻기 위해 Cz-공정의 최적화된 설계를 구성하였다. 결정 성장 시뮬레이션로부터 결정성장을 위한 Pulling rate 및 Rotation speed에 최적의 변수값을 형성하기 위해 사용되었으며, 변형된 Cz-공정에 대한 연구 및 해당 결과가 논의되며 결정 성장 시뮬레이션을 사용하여 Cz-공정의 Pulling rate, Rotation speed 및 Melt charge level의 최적화된 설계로 인한 결정성장시 단결정 실리콘으로 유입되는 산소 농도 최소화를 설계하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.361.2-361.2
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• 2014

Transition metal dichalcogenides (MoS2, WS2, WSe2, MoSe2, NbS2, NbSe2, etc.) are layered materials that can exhibit semiconducting, metallic and even superconducting behavior. In the bulk form, the semiconducting phases (MoS2, WS2, WSe2, MoSe2) have an indirect band gap. Recently, these layered systems have attracted a great deal of attention mainly due to their complementary electronic properties when compared to other two-dimensional materials, such as graphene (a semimetal) and boron nitride (an insulator). However, these bulk properties could be significantly modified when the system becomes mono-layered; the indirect band gap becomes direct. Such changes in the band structure when reducing the thickness of a WS2 film have important implications for the development of novel applications, such as valleytronics. In this work, we report for the controlled synthesis of large-area (~cm2) single-, bi-, and few-layer WS2 using a two-step process. WOx thin films were deposited onto a Si/SiO2 substrate, and these films were then sulfurized under vacuum in a second step occurring at high temperatures ($750^{\circ}C$). Furthermore, we have developed an efficient route to transfer these WS2 films onto different substrates, using concentrated HF. WS2 films of different thicknesses have been analyzed by optical microscopy, Raman spectroscopy, and high-resolution transmission electron microscopy.