• Proceedings of the KIPE Conference
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• 2001.12a
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• pp.185-189
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• 2001

This paper presents a precision voltage control technique of a single phase PWM inverter for a constant voltage and constant frequency(CVCF) applications. The proposed control employes a PLL compensating loop which minimize the steady state error and phase delay. The computer simulation and experiment are carried out for the actual single phase PWM inverter and the results well demonstrate the effectiveness of the proposed control.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.12
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• pp.136-145
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• 2009

This paper proposes control methods and simulation models of a driving system, which consists of converters and inverters, for high speed trains employing multi-level power converters. The control method of a single phase three-level converter for high-speed trains is designed to use DC values instead of instantaneous current values which are usually used in single-phase application, so that it results in a fast and robust voltage control response. In addition, simulation models of Space Vector Pulse Width Modulation (SVPWM) for single phase three-level converters as well as three level inverters are proposed. Experimental results demonstrate the validity of the simulation model for three-level inverters.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.5
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• pp.718-725
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• 2015

This paper proposes a novel level-shifted PWM (LS-PWM) strategy for fault tolerant cascaded multilevel inverter. Most proposed fault-tolerant operation methods in many of studies are based on a phase-shifted PWM (PS-PWM) method. To apply these methods to multilevel inverter systems using LS-PWM, two additional steps will be implemented. During the occurrence of a single-inverter-cell fault, the carrier bands scheme is reconfigured and modulation levels of inverter cells are reassigned in this proposed fault-tolerant operation. The proposed strategy performs balanced three-phase line-to-line voltages and line currents when a switching device fault occurs in a cascaded multilevel inverter using LS-PWM. Simulation and experimental results are included in the paper to verify the proposed method.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1227-1234
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• 2015

The efficient electric power demand management in electric power supply industry is currently being changed by distributed generation. Meanwhile, small-scale distributed generation systems using renewable energy are being constructed worldwide. Several small-scale renewable distributed generation systems, which can supply electricity to the grid at peak load of the grid as per policy such as demand response programs, could help in the stability of the electric power demand management. In this case, the power quality of the small-scale renewable distributed generation system is more significant. Low prices of power semiconductors and multilevel inverters with high power quality have been recently investigated. However, the conventional multilevel inverter topology is unsuitable for the small-scale renewable distributed generation system, because the number of devices of such topology increases with increasing output voltage level. In this paper, a single-phase multilevel inverter based on H-bridge, with DC_Link divided by bi-directional switches, is proposed. The proposed topology has almost half the number of devices of the conventional multilevel inverter topology when these inverters have the same output voltage level. Double Fourier series solution is mainly used when comparing PWM output harmonic components of various inverter topologies. Harmonic components of the proposed multilevel inverter, which have been analyzed by double Fourier series, are compared with those of the conventional multilevel inverter. An inverter prototype is then developed to verify the validity of the theoretical analysis.

• Journal of Power Electronics
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• v.19 no.1
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• pp.44-57
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• 2019

Recently, the use of LLCL filters for grid inverters has been suggested to give better harmonic attenuation than the commonly used L and LCL filters, particularly around the switching frequency. Nevertheless, this filter is mainly designed for constant switching frequency pulse width modulation (CSF PWM) methods. In variable switching frequency PWM (VSF PWM), the harmonic components are distributed across a wide frequency band which complicates the use of a high order filter, including LCL and LLCL filters. Recently, a confined band variable switching frequency (CB-VSF) PWM method has been proposed and demonstrated to be superior to the conventional constant switching frequency (CSF) PWM in terms of switching losses. However, the applicability of LLCL filters for this type of CB-VSF PWM has not been discussed. In this paper, the authors study the suitability of an LLCL filter for CB-VSF PWM and propose design guidelines for the filter parameters. Using simulation and experimental results, it is demonstrated that the effectiveness of an LLCL filter with CB-VSF PWM depends on the parameters of the filters as well as the designed variable frequency band of the PWM. Simulation results confirm the performance of the suggested LLCL design, which is further validated using a lab scale prototype.

• Journal of the Korean Society for Railway
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• v.20 no.4
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• pp.448-457
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• 2017

In this paper, for high speed railway propulsion systems, a single phase PWM Converter using discontinuous PWM (DPWM) was investigated. The conventional PWM Converter uses a low frequency modulation index of less than 10 to reduce switching losses due to high power characteristics, which results in low control frequency bandwidth and requires an additional compensation method. To solve these problems, the DPWM method, which is commonly used in three phase PWM Inverters, was adopted to a single phase PWM Converter. The proposed method was easily implemented using offset voltage techniques. Method can improve the control performance by doubling the frequency modulation index for the same switching loss, and can also bring the same dynamic characteristics among switches. Proposed DPWM method was verified by simulation of 100 kW PWM converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.4
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• pp.275-282
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• 2022

In this study, an inverter system connected to a grid through a paralleled LCL filter is proposed. The system consists of two inverters paralleled and operated with interleaved PWM for powering up and performance improvement. Two LCL filters have two separate filter inductors and one set of filter capacitor and grid inductor in common. The differential mode current circulates through two inverters and two filter inductors. The differential mode current is removed from the filter capacitor and the power grid. Accordingly, performance improvement can be achieved due to the reduced currents in the filter capacitor and the reduced harmonics into a grid. A single-phase prototype has been made and tested, and the proposal has been verified.

• Journal of Power Electronics
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• v.17 no.1
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• pp.106-114
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• 2017

In this paper, the Selective Harmonic Mitigation-PWM (SHM-PWM) method is used in single-phase and three-phase Cascaded H-Bridge (CHB) inverters in order to fulfill different power quality standards such as EN 50160, CIGRE WG 36-05, IEC 61000-3-6 and IEC 61000-2-12. Non-equal DC link voltages are used to increase the degrees of freedom for the proposed SHM-PWM technique. In addition, it will be shown that the obtained solutions become continuous and without sudden changes. As a result, the look-up tables can be significantly reduced. The proposed three-phase modulation method can mitigate up to the 50th harmonic from the output voltage, while each switch has just one switching in a fundamental period. In other words, the switching frequency of the power switches are limited to 50 Hz, which is the lowest switching frequency that can be achieved in the multilevel converters, when the optimal selective harmonic mitigation method is employed. In single-phase mode, the proposed method can successfully mitigate harmonics up to the 50th, where the switching frequency is 150 Hz. Finally, the validity of the proposed method is verified by simulations and experiments on a 9-level CHB inverter.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.3
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• pp.244-251
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• 2010

High speed motors have been widely used in industries to reduce system size and improve power conversion efficiency. However, the high speed motors sometimes suffer from core losses caused by PWM current ripple; noting that the phase inductance, $L_s$, of high speed motor is smaller than that of ordinary motors. In the proposed topology, three PWM inverters are connected in parallel through nine coupled inductors. Compared to the PWM current ripple of the conventional single inverter system, that of the proposed scheme can be conspicuously reduced without the voltage drop at the inductors. In this paper a theoretical analysis of the output voltage of the proposed topology is presented, and then the validity of the proposed method is verified by experimental results.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.3
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• pp.252-258
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• 2010

If the speed measurement of resolver and the generation of PWM signals are implemented with single microcontroller, it is easy to reduce the system cost and to avoid the switching noise of inverters. To avoid the switching noise and to improve the accuracy of measurement, PWM switching and A/D sampling of the resolver should be synchronized. Phase angle of the resolver excitation signal is increased in stepwise manner, then, the output signal of the resolver is measured in each step. From the measured data, the optimal phase angle of resolver excitation signal is estimated using the least square approximation method.