• Proceedings of the KIEE Conference
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• 2003.07b
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• pp.1235-1237
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• 2003

For small capacity rectifier circuits as these for consumer electronics and appli capacitor input type rectifier circuits are gen used. Consequently. various harmonics gen within the power system become a serious pro Various studies of this effect have been pres previously. However. most of these employ swit devices, such as FETs and the like. The absen switching devices makes systems more toleran over -load, and brings low radio noise benefits propose a power factor correction scheme using resonant in commercial frequency without swit devices. In this method. It makes a sinusoidal by widening conduction period using the cu resonance in commercial frequency. Hence, harmonic characteristics can be significantly imp where the lower order harmonics. such as the and seventh orders are much reduced. The resu confirmed by the theoretical and experm implementations.

• Journal of Power Electronics
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• v.12 no.1
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• pp.104-112
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• 2012

In this paper a new method for the design of a simple PI controller is presented and it has been applied in the control of a Boost based PFC rectifier. The Strength Pareto evolutionary algorithm, which is based on the Pareto Optimality concept, used in Game theory literature is implemented as a multi-objective optimization approach to gain a good transient response and a high quality input current. In the proposed method, the input current harmonics and the dynamic response have been assumed as objective functions, while the PI controller's gains of the PFC rectifier (Kpi, Tpi) are design variables. The proposed algorithm generates a set of optimal gains called a Pareto Set corresponding to a Pareto Front, which is a set of optimal results for the objective functions. All of the Pareto Front points are optimum, but according to the design priority objective function, each one can be selected. Simulation and experimental results are presented to prove the superiority of the proposed design methodology over other methods.

• Proceedings of the KIPE Conference
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• 2011.11a
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• pp.169-170
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• 2011

PFC(Power Factor Correction) converters are commonly designed for CCM(Continuous Conduction Mode). However, DCM(Discontinuous Conduction Mode) appears in the input current near the ZCP(Zero Crossing Point) at light loads, resulting in input current distortion. It is caused by inaccurate average current values obtained in DCM. This paper studies a simple digital control scheme that can be operated in both CCM and DCM with minimal changes to the CCM average current control structure.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.6
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• pp.57-65
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• 2007

This paper presents the design of single phase PFC(Power Factor Correction) using a DSP(TMS320F2812). In order to realize the proposed boost PFC converter in average current mode control, the DSP requires the A/D sampling values for a line input voltage, a inductor current, and the output voltage of the converter. Because of a FET switching noise, these sampling values contain a high frequency noise and switching ripple. The solution of A/D sampling keeps away from the switching point. Because the PWM duty is changed from 5% to 95%, we can#t decide a fixed sampling time. In this paper, the three A/D converters of the DSP are started using the prediction algorithm for the FET ON/OFF time at every sampling cycle(40 KHz). Implemented A/D sampling algorithm with only one timer of the DSP is very simple and gives the autostart of these A/D converters. From the experimental result, it was shown that the power factor was about 0.99 at wide input voltage, and the output ripple voltage was smaller than 5 Vpp at 80 Vdc output. Finally the parameters and gains of PI controllers are controlled by serial communication with Windows Xp based PC. Also it was shown that the implemented PFC converter can achieve the feasibility and the usefulness.

• Journal of Power Electronics
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• v.3 no.4
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• pp.249-258
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• 2003

This paper presents a high-efficient and cost effective three-phase AC/DC-DC/AC power conversion system with a single two-switch type active Auxiliary Resonant DC Link (ARDCL) snubber circuit, which can minimize the total power dissipation. The active ARDCL snubber circuit is proposed in this paper and its unique features are described. Its operation principle in steady-state is discussed for the three phase AC/DC-DC/AC converter, which is composed of PWM rectifier as power factor correction (PFC) converter, sinewave PWM inverter. In the presented power converter system not only three-phase AC/DC PWM rectifier but also three-phase DC/AC inverter can achieve the stable ZVS commutation for all the power semiconductor devices. It is proved that the proposed three-phase AC/DC-DC/AC converter system is more effective and acceptable than the previous from the cost viewpoint and high efficient consideration. In addition, the proposed two-switch type active auxiliary ARDCL snubber circuit can reduce the peak value of the resonant inductor injection current in order to maximize total system actual efficiency by using the improved DSP based control scheme. Moreover the proposed active auxiliary two-switch ARDCL snubber circuit has the merit so that there is no need to use any sensing devices to detect the voltage and current in the ARDCL sunbber circuit for realizing soft-switching operation. This three-phase AC/DC-DC/AC converter system developed for UPS can achieve the 1.8% higher efficiency and 20dB lower conduction noise than those of the conventional three-phase hard-switching PWM AC/DC-DC/AC converter system. It is proved that actual efficiency of the proposed three-phase AC/DC-DC/AC converter system operating under a condition of soft switching is 88.7% under 10kw output power.