• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 제13회 신호처리 합동 학술대회 논문집
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• pp.505-508
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• 2000

본 논문에서는 16채널 혹은 8채널의 센서를 통해 들어오는 저주파대역의 아날로그 신호를 수집하고. 수집된 데이터를 실시간으로 처리하기 위한 고속의 신호처리 기능이 결합된 통합 DSP (Digital Signal Processor)시스템을 구현하였다. 구현된 시스템은 휴대가 용이하도록 소형으로 설계되어 있으며 노트북 등의 이동형 장비에 활용되도록 USB 인터페이스를 채택하였으며, 장치간의 네트워크 구성이 가능하도록 Ethernet 인터페이스를 추가하였다 Digital Signal Processor는 Texas Instrument 사의 TMS320C6701 부동소수점 연산방식의 고성능 DSP를 사용하여 16채널의 실시간 신호 분석이 가능하게 하였으며, ICP 센서 구동용 전류 공급부를 내장하여 센서 선택의 폭을 넓히었고, programmable gain amplifier인 PGA202증폭기를 사용하여 입력신호가 작을 경우 최대 1000배, 즉 60dB까지 입력신호를 증폭하여 수집 및 분석할 수 있다. 200kSPS의 샘플링 레이트와 16bit resolution을 가지는 AD976 A/D converter를 사용하여 채널당 0～6kHz의 신호대역폭을 가지며,differential 입력시 8 채널,single ended 입력시 16 채널의 입력 신호의 수집 및 분석이 가능하다. Windows 응용프로그램에서는 사용자가 원하는 입력신호 및 스펙트럼 실시간 분석, 입력신호 기록 및 저장, RPM 측정 및 분석, 외부 트리거 및 레벨 트리거를 이용한 입력신호 제어와 수집된 데이터를 바탕으로 원하는 제어가 가능한 응용프로그램 제작에 활용될 라이브러리가 포함된다.

• Journal of electromagnetic engineering and science
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• 제4권3호
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• pp.137-142
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• 2004

In this paper, we present a new current-current negative feedback(CCNF) differential voltage-controlled oscillator (VCO) with 1/f induced low-frequency noise suppressed. By means of the CCNF, the 1/f induced low-frequency noise is removed from the proposed CCNF VCO. Also, high-frequency noise is stopped from being down-converted into phase noise by means of the increased output impedance through the CCNF and the feedback capacitor $C_f. The proposed CCNF VCO represents 11-dB reduction in phase noise at 10 kHz offset, compared with the conventional differential VCO. The phase noise of the proposed CCNF VCO is measured as - 87 dBc/Hz at 10 kHz offset frequency from 5.5-GHz carrier. The proposed CCNF VCO consumes 14.0 mA at 2.0 V supply voltage, and shows single-ended output power of - 12 dBm.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.278-285
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• 2012

A digital readout IC for capacitive sensors is presented. Digital capacitance readout circuits suffer from static capacitance of sensors, especially single-ended sensors, and require large passive elements to cancel such DC offset signal. For this reason, to maximize a dynamic range with a small die area, the proposed circuit features digital filters having a coarse and fine compensation steps. Moreover, by employing switched-capacitor circuit for the front-end, correlated double sampling (CDS) technique can be adopted to minimize low-frequency device noise. The proposed circuit targeted 8-kHz signal bandwidth and oversampling ratio (OSR) of 64, thus a $3^{rd}$-order ${\Delta}{\Sigma}$ modulator operating at 1 MH was used for pulse-density-modulated (PDM) output. The proposed IC was designed in a 0.18-${\mu}m$ CMOS mixed-mode process, and occupied $0.86{\times}1.33mm^2$. The measurement results shows suppressed DC power under about -30 dBFS with minimized device flicker noise.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 추계학술대회 논문집
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• pp.133-135
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• 2007

This research presented the new zero-current switching pulse width modulation SEPP(Single Ended Push-Pull)high frequency inverter for solving the problem of the zero-current SEPP high frequency inverter circuit which is using widely in the practical application of an induction heating apparatus, the soft switching operation and power control are impossible when the lowest power supply in the zero-current switching pulse width modulation SEPP high frequency inverter. The inverter circuit which is attempted by on-off operation of a switch has the reduction effect of the power loss due to a soft switching and a high frequency switching. And it confirmed that the power regulation is possible continuously from 0.25[kW] until 2.84[kW] in the case the duty rate(D) changes from 0.08 to 0.3 under zero-current switching operating by a dissymmetry pulse width modulating control and the power conversion efficiency comes true the efficiency of 95[%]. Due to the result above, the ZCS PWM SEPP high frequency inverter will be effective as sources of an induction heating apparatus.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 학술대회 논문집 전문대학교육위원
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• pp.119-124
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• 2007

This research presented the new zero-current switching pulse width modulation SEPP(Single Ended Push-Pull)high frequency inverter for solving the problem of the zero-current SEPP high frequency inverter circuit which is using widely in the practical application of an induction heating apparatus, the soft switching operation and power control are impossible when the lowest power supply in the zero-current switching pulse width modulation SEPP high frequency inverter. The inverter circuit which is attempted by on-off operation of a switch has the reduction effect of the power loss due to a soft switching and a high frequency switching. And it confirmed that the power regulation is possible continuously from 0.25[kW] until 2.84[kW] in the case the duty rate(D) changes from 0.08 to 0.3 under zero-current switching operating by a dissymmetry pulse width modulating control and the power conversion efficiency comes true the efficiency of 95[%]. Due to the result above, the ZCS PWM SEPP high frequency inverter will be effective as sources of an induction heating apparatus.

• 전자공학회논문지
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• 제49권12호
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• pp.219-225
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• 2012

디지털 보청기용 저전력, 저잡음 전치증폭기를 설계하였다. 본 전치증폭기는 일렛트렛 마이크로부터 싱글엔드 형태로 입력 받은 신호를 증폭한 후, 차동신호의 형태로 ADC에 전달한다. 또, 3.6, 7.2, 14.4, 28.8의 가변이득을 가지며 100Hz~10kHz의 주파수 대역에서 동작한다. 설계된 증폭기는 130nm CMOS 공정으로 제작되었으며, 1.2V 전원을 사용하여 측정한 결과 85dB의 SNR, 0.05%의 고조파 왜곡 및 $200{\mu}W$의 파워소모를 얻었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.160-165
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• 2009

A 12b 2 MS/s cyclic ADC processing 3.3 Vpp single-ended rail-to-rail input signals is presented. The proposed ADC demonstrates an offset voltage less than 1 mV without well-known calibration and trimming techniques although power supplies are directly employed as voltage references. The SHA-free input sampling scheme and the two-stage switched op-amp discussed in this work reduce power dissipation, while the comparators based on capacitor-divided voltage references show a matched full-scale performance between two flash sub ADCs. The prototype ADC in a $0.18{\mu}m$ 1P6M CMOS demonstrates the effective number of bits of 11.48 for a 100 kHz full-scale input at 2 MS/s. The ADC with an active die area of $0.12\;mm^2$ consumes 3.6 m W at 2 MS/s and 3.3 V (analog)/1.8 V (digital).

• Animal cells and systems
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• 제2권4호
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• pp.501-506
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• 1998

In the goby Micropercops swinhonis, the development of its egg's enveloping layers could be divided into 4 stages. In the earliest developmental period, stage I, there is a simple oocyte surrounded by a layer of squamous follicular cells. Stage II corresponds to the yolk vesicle stage of vitellogenesis. Here the initial follicular layer has become bilaminar with the retention of its outer squamous cell layer and the acquisition of an inner cuboidal cell layer just over the zona radiata. The number and size of the cuboidal cells increases throughout this stage. Stage III corresponds to the yolk granule stage of true vitellogenesis. Here the cuboidal cells begin to be replaced by columnar cells. As the oocyte grows, the columnar cells increase in size. The columnar cells produce cytoplasmic neutral mucins and by the end of this stage their cytoplasm has been filled with this mucin. In stage IV a single layer of squamous cells still remained as the outer follicular layer of the oocyte. The secretory activity of the inner follicular layers' columnar cells has ceased and they had lost their cell wall integrity and ended as a series of bullet-shaped, neutral mucin deposits.

• Journal of Power Electronics
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• 제2권3호
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• pp.181-188
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• 2002

The utility interfaced sinewave modulation Inverter for the solar photovoltaic power conditioner with a high frequency transformer is presented for residential applications. As compared with the conventional full-bridge hard switching slnewave PWM inverter with a high frequency link, the simplest single-ended edge-resonant soft switching sinewave inverter with a sinewave duty cycle pulse control scheme is implemented, resulting in size and weight reduction, low cost and high efficiency This paper presents a prototype system of the sinewave zero voltage soft switching sinewave inverter for solar power conditioner, along with its operating principle and unique features. In addition to these, this paper discusses a control implementation to deliver high quality output current. Major design of each component and the power loss analysis under actual power processing is also discussed and evaluated from an experimental point of view A newly developed utility-connected sinewave power conditioning circuit which achieves 92.5% efficiency under 4kW output is demonstrated.

• 대한의용생체공학회:의공학회지
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• 제26권4호
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• pp.215-221
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• 2005

We describe the development of a prototype multi-channel electrical impedance tomography (EIT) system. The EIT system can be equipped with either a single-ended current source or a balanced current source. Each current source can inject current between any chosen pair of electrodes. In order to reduce the data acquisition time, we implemented multiple digital voltmeters simultaneously acquiring and demodulating voltage signals. Each voltmeter measures a differential voltage between a fixed pair of adjacent electrodes. All voltmeters are configured in a radially symmetric architecture to optimize the routing of wires and minimize cross-talks. To maximize the signal-to-noise ratio, we implemented techniques such as digital waveform generation, Howland current pump circuit with a generalized impedance converter, digital phase-sensitive demodulation, tri-axial cables with both grounded and driven shields, and others. The performance of the EIT system was evaluated in terms of common-mode rejection ratio, signal-to-noise ratio, and reciprocity error. Future design of a more innovative EIT system including battery operation, miniaturization, and wireless techniques is suggested.