• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.86.5-86
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• 2001

This work describes a design and implementation of the level & flow rate control system by using a single-chip microcontroller. The proposed model system is designed based on the use of the single-chip microcontroller 8031 with the EPROM emulator for programming the computer software. The microcontroller reaches the input level and flow signals from the level sensor and the turbine flowmeter, respectively, via the signal conditioning circuits and A/D converters in order to calculate the control signal. Moreover, the status of the process variable can easily be set up and controlled by program monitoring through the emulator, and can be graphically displayed on the computer screen. Experiment results were carried out which can be ...

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.6
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• pp.241-246
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• 2021

In this paper, we developed the evaluation system for the active noise control so that the algorithms can be easily evaluated in real-time on the system. We implemented the active noise controller based on a single-chip with only additional op-amps for signal conditioning because the TMS320C280049 MCU includes almost all necessary peripherals for the active noise controller. Due to the difficulty in testing algorithms on embedded-type hardware unlike in computer simulation, we also developed GUI-based evaluation software which makes it simple to test algorithms on the hardware. Using the GUI software, we can optimize the parameters of the algorithms with ease in a specific noise environment because the parameters can be adjusted in real-time when the algorithm is running on the hardware.

• Journal of information and communication convergence engineering
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• v.18 no.4
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• pp.245-253
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• 2020

The human body and nervous system transmit information through electric charges. After the electric charge transmits information to the brain, we can feel pain, numbness, comfort, and other feelings. Electric therapy is currently used widely in clinical practice because the field of examination is more representative of electrocardiogram, and in the field of treatment is more representative of electrotherapy. In this study, we design a system for neurophysiological therapy and conduct parameter calculation and model selection for the components of the system. The system is based on a discontinuous conduction mode (DCM) boost circuit, and controlled and regulated by a single-chip microcomputer. The system does not only have a low cost but also fully considers the safety of use, convenience of the human-computer interface, adjustment sensitivity, and waveform diversity in the design. In future, it will have strong implications in the field of electrotherapy.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Proceedings of the KIPE Conference
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• 1997.07a
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• pp.374-376
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• 1997

This paper presents a 3kW grid-connection photovolatic power generation system and its simple topology. The system controlled by single chip micropocessor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.68-75
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• 2007

A single chip NFC transceiver supporting not only NFC active and passive mode but also 13.56MHz RFID reader and tag mode was designed and fabricated. The proposed NFC transceiver can operate as a RFID tag even without external power supply which has dual antenna structure for initiator and target. The area increment due to additional target antenna is negligible because the target antenna is constructed by using a shielding layer of initiator antenna. The analog front end circuit of the proposed NFC transceiver consists of a transmitter and receiver of reader/writer block supporting NFC initiator or RFID reader mode, and a tag circuit for target of passive NFC mode or RFID tag mode. The maximum baud rate of the proposed NFC device is 212kbps by using UART serial interface. The chip has been designed and fabricated using a Magnachip's $0.35{\mu}m$ double poly 4-metal CMOS process, and the effective area of the chip is 2200um by 3600um.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.65-73
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• 2002

In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.12
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• pp.1671-1674
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• 2014

This paper presents a frequency-dependent cell impedance analysis chip for use in cancer and normal cell discrimination. The previous cell impedance analysis chips for flowing cells cannot allow enough time for cell-to-electrode contact to monitor frequency-dependent impedance response. Another type of the previous cell impedance analysis chips for the cells clamped by membranes need complex sample control for making stable cell-to-electrode contact. We present a new impedance analysis chip using the microchamber array, on which a PDMS cover is placed to make stable cell-to-electrode contact for the individual cell trapped in each microchamber; thus achieving frequency-dependent single-cell impedance analysis without complex sample control. Compared to the normal cells, the magnitude of NHBE cells is $60.07{\sim}97.41k{\Omega}$ higher than A549 cells in the frequency range of 95.6 kHz~2MHz and the phase of NHBE is $3.96^{\circ}{\sim}20.8^{\circ}$ higher than A549 cells in the frequency range of 4.37 kHz~2MHz, respectively. It is demonstrated experimentally that the impedance analysis chip performs frequency-dependent cell impedance analysis by making stable cell-to-electrode contact with simple sample control; thereby applicable to the normal cell and cancer cell discrimination.

• Journal of KIISE
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• v.42 no.8
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• pp.961-971
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• 2015

As a representative area-decomposed algorithm, an area-based quad-trie (AQT) has an issue of search performance. The search procedure must continue to follow the path to its end, due to the possibility of the higher priority-matching rule, even though a matching rule is encountered in a node. A leaf-pushing AQT improves the search performance of the AQT by making a single rule node exist in each search path. This paper proposes a new algorithm to further improve the search performance of the leaf-pushing AQT. The proposed algorithm implements a leaf-pushing AQT using a hash table and an on-chip Bloom filter. In the proposed algorithm, by sequentially querying the Bloom filter, the level of the rule node in the leaf-pushing AQT is identified first. After this procedure, the rule database, which is usually stored in an off-chip memory, is accessed. Simulation results show that packet classification can be performed through a single hash table access using a reasonable sized Bloom filter. The proposed algorithm is compared with existing algorithms in terms of the memory requirement and the search performance.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.2
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• pp.461-468
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• 2010

This paper presents a simple digital LCD backlight inverter using a single-chip microcontroller. The proposed inverter reduces the ignition voltage and eliminates the current spikes and hence improves the ignition behavior of the cold cathode fluorescent lamp(CCFL). Thus it increases the CCFL's life span. This is achieved by implementing a digital dimming control algorithm, that contains the soft-starting algorithm, all on a single-chip microcontroller. The inverter utilizes the full-bridge resonant circuit topology. The design example along with a simple analysis for the inverter is shown, and the experimental results of the designed prototype results in close agreement with the theoretical analysis and explanation. The overall system's power efficiency is approximately 85%. Compared with conventional inverters, the ignition voltage is reduced by around 30% without any lamp current spike occurring during the dimming control operation.