• Journal of IKEEE
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• v.26 no.2
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• pp.160-168
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• 2022

In this paper, we propose a 3D mesh reconstruction method from a single image using deep learning and a sphere shape transformation method. The proposed method has the following originality that is different from the existing method. First, the position of the vertex of the sphere is modified to be very similar to the 3D point cloud of an object through a deep learning network, unlike the existing method of building edges or faces by connecting nearby points. Because 3D point cloud is used, less memory is required and faster operation is possible because only addition operation is performed between offset value at the vertices of the sphere. Second, the 3D mesh is reconstructed by covering the surface information of the sphere on the modified vertices. Even when the distance between the points of the 3D point cloud created by correcting the position of the vertices of the sphere is not constant, it already has the face information of the sphere called face information of the sphere, which indicates whether the points are connected or not, thereby preventing simplification or loss of expression. can do. In order to evaluate the objective reliability of the proposed method, the experiment was conducted in the same way as in the comparative papers using the ShapeNet dataset, which is an open standard dataset. As a result, the IoU value of the method proposed in this paper was 0.581, and the chamfer distance value was It was calculated as 0.212. The higher the IoU value and the lower the chamfer distance value, the better the results. Therefore, the efficiency of the 3D mesh reconstruction was demonstrated compared to the methods published in other papers.

• Journal of Broadcast Engineering
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• v.26 no.4
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• pp.429-440
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• 2021

With the recent development of deep convolutional neural network learning, deep learning techniques applied to single image super-resolution are showing good results. One of the existing deep learning-based super-resolution techniques is RDN(Residual Dense Network), in which the initial feature information is transmitted to the last layer using residual dense blocks, and subsequent layers are restored using input information of previous layers. However, if all hierarchical features are connected and learned and a large number of residual dense blocks are stacked, despite good performance, a large number of parameters and huge computational load are needed, so it takes a lot of time to learn a network and a slow processing speed, and it is not applicable to a mobile system. In this paper, we use the residual dense structure, which is a continuous memory structure that reuses previous information, and the residual dense channel attention block using the channel attention method that determines the importance according to the feature map of the image. We propose a method that can increase the depth to obtain a large receptive field and maintain a concise model at the same time. As a result of the experiment, the proposed network obtained PSNR as low as 0.205dB on average at 4× magnification compared to RDN, but about 1.8 times faster processing speed, about 10 times less number of parameters and about 1.74 times less computation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.17 no.4
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• pp.266-274
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• 2024

In this paper, we designed a low-area 32-bit PF (Poly-fuse) OTP IP, a non-volatile memory that stores data required for analog circuit trimming and calibration. Since one OTP cell is constructed using two PFs in one select transistor, a 1cell-2bit multibit PF OTP cell that can program 2bits of data is proposed. The bitcell size of the proposed 1cell-2bit PF OTP cell is 1/2 of 12.69㎛ × 3.48㎛ (=44.161㎛2), reducing the cell area by 33% compared to that of the existing PF OTP cell. In addition, in this paper, a new 1 row × 32 column cell array circuit and core circuit (WL driving circuit, BL driving circuit, BL switch circuit, and DL sense amplifier circuit) are proposed to meet the operation of the proposed multbit cell. The layout size of the 32bit OTP IP using the proposed multibit cell is 238.47㎛ × 156.52㎛ (=0.0373㎛2) is reduced by about 33% compared that of the existing 32bit PF OTP IP using a single bitcell, which is 386.87㎛ × 144.87㎛ (=0.056㎛2). The 32-bit PF OTP IP, designed with 10 years of data retention time in mind, is designed with a minimum programmed PF sensing resistance of 10.5㏀ in the detection read mode and of 5.3 ㏀ in the read mode, respectively, as a result of post-layout simulation of the test chip.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.8 no.2
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• pp.193-204
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• 1998

The single crystal of the $LiTaO_3$has large electro-optic effects, so it is applied to optical switch, acousto-optic deflector, and optical memory device as hologram using photorefractive effect. In this study, optic-grade undoped $LiTaO_3$and Fe:LiTaO$LiTaO_3$single crystals were grown by the Czochralski method and optical transmission and absorption spectrums were measured in the wavelength of UV-VIS range. The curie temperature was determined with DSC and by measuring capacitance for the grown undoped crystal and ceramic powder samples of various Li/Ta ratio. In case of having a 48.6 mol% $Li_2O$ as a starting Li/Ta ratio, the results of concentration variations were below 0.01 mol% $Li_2O$ all over the crystal, so it was confirmed that $LiTaO_3$single crystals were grown under congruent melting composition having optical homogeneity. The curie temperature of the Fe:$LiTaO_3$crystal was increased with increased with increased doped Fe concentrations;by the ratio of $7.5^{\circ}C$ increase per Fe 0.1 wt%. Also, the optical transmittance was about 78 %, which was sufficient for optical device.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.40 no.3
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• pp.273-283
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• 2020

Because of climate change, the occurrence of localized and heavy rainfall is increasing. It is important to predict floods in urban areas that have suffered inundation in the past. For flood prediction, not only numerical analysis models but also machine learning-based models can be applied. The LSTM (Long Short-Term Memory) neural network used in this study is appropriate for sequence data, but it demands a lot of data. However, rainfall that causes flooding does not appear every year in a single urban basin, meaning it is difficult to collect enough data for deep learning. Therefore, in addition to the rainfall observed in the study area, the observed rainfall in another urban basin was applied in the predictive model. The LSTM neural network was used for predicting the total overflow, and the result of the SWMM (Storm Water Management Model) was applied as target data. The prediction of the inundation map was performed by using logistic regression; the independent variable was the total overflow and the dependent variable was the presence or absence of flooding in each grid. The dependent variable of logistic regression was collected through the simulation results of a two-dimensional flood model. The input data of the two-dimensional flood model were the overflow at each manhole calculated by the SWMM. According to the LSTM neural network parameters, the prediction results of total overflow were compared. Four predictive models were used in this study depending on the parameter of the LSTM. The average RMSE (Root Mean Square Error) for verification and testing was 1.4279 ㎥/s, 1.0079 ㎥/s for the four LSTM models. The minimum RMSE of the verification and testing was calculated as 1.1655 ㎥/s and 0.8797 ㎥/s. It was confirmed that the total overflow can be predicted similarly to the SWMM simulation results. The prediction of inundation extent was performed by linking the logistic regression with the results of the LSTM neural network, and the maximum area fitness was 97.33 % when more than 0.5 m depth was considered. The methodology presented in this study would be helpful in improving urban flood response based on deep learning methodology.

• Korean Journal of Optics and Photonics
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• v.18 no.5
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• pp.351-361
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• 2007

The samples composed of a GST thin film and the protective layers of $ZnS-SiO_2$ or $Al_2O_3$ coated on c-Si substrate were prepared by using the magnetron sputtering method. Samples of three different structures were prepared, that is, i) the GST single film on c-Si substrate, ii) the GST film sandwiched by the protective $ZnS-SiO_2$ layers on c-Si substrate, and iii) the GST film sandwiched by $Al_2O_3$ protective layers on c-Si substrate. The ellipsometric constants in the temperature range from room temperature to $700^{\circ}C$ were obtained by using the in-situ ellipsometer equipped with a conventional heating chamber. The measured ellipsometric constants show strong variations versus temperature. The variation of ellipsometric constants at the temperature region higher than $300^{\circ}C$ shows different behaviors as the ambient medium is changed from in air to in vacuum or the protective layers are changed from $ZnS-SiO_2$ to $Al_2O_3$. Since the long heating time of 1-2 hours is believed to be the origin of the high temperature variation of ellipsometric constants upon the heating environment and the protective layers, a PRAM (Phase-Change Random Access Memory) recorder is introduced to reduce the heating time drastically. By using the PRAM recorder, the GST samples are heated up to $700^{\circ}C$ decomposed preventing its partial evaporation or chemical reactions with adjacent protective layers. The surface image obtained by SEM and the surface micro-roughness verified by AFM also confirmed that samples prepared by the PRAM recorder have smoother surface than the samples prepared by using the conventional heater.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.3
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• pp.82-90
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• 2011

Multi-core system is becoming more general with development of microprocessors. Due to this change in performance improvement paradigm, switching conventional single thread applications with multi thread applications. Performance monitoring tools are used to optimize application performance because of complexity in development of multi thread applications. Conventional performance monitoring tools are focused on performance itself rather than user friendliness or real-time support. Real-time performance monitor identify the problem while multi-threaded applications should be performed as well as check real-time operating status of the application. So it can be used as an effective tool compared to non-real-time performance monitor that only with simple performance indicators to find the cause of the problem. In this paper, we propose RMPM(Real-time Multi-core Performance Monitor) which is real-time performance monitoring tool for multi-core system. Observation period is optimized by comparing relation between overhead due to performance evaluation period and accuracy. Our performance monitor shows not only amount of CPU usage of whole system, memory usage, network usage but also aspect of overhead distribution per thread of an application.

• The Korean Journal of Physiology and Pharmacology
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• v.24 no.1
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• pp.11-18
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• 2020

The present study was aimed to explore the neuroprotective role of imatinib in global ischemia-reperfusion-induced cerebral injury along with possible mechanisms. Global ischemia was induced in mice by bilateral carotid artery occlusion for 20 min, which was followed by reperfusion for 24 h by restoring the blood flow to the brain. The extent of cerebral injury was assessed after 24 h of global ischemia by measuring the locomotor activity (actophotometer test), motor coordination (inclined beam walking test), neurological severity score, learning and memory (object recognition test) and cerebral infarction (triphenyl tetrazolium chloride stain). Ischemia-reperfusion injury produced significant cerebral infarction, impaired the behavioral parameters and decreased the expression of connexin 43 and phosphorylated signal transducer and activator of transcription 3 (p-STAT3) in the brain. A single dose administration of imatinib (20 and 40 mg/kg) attenuated ischemia-reperfusion-induced behavioral deficits and the extent of cerebral infarction along with the restoration of connexin 43 and p-STAT3 levels. However, administration of AG490, a selective Janus-activated kinase 2 (JAK2)/STAT3 inhibitor, abolished the neuroprotective actions of imatinib and decreased the expression of connexin 43 and p-STAT3. It is concluded that imatinib has the potential of attenuating global ischemia-reperfusion-induced cerebral injury, which may be possibly attributed to activation of JAK2/STAT3 signaling pathway along with the increase in the expression of connexin 43.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.4
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• pp.68-74
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• 2017

This paper presents a joint demosaicking and arbitrary-ratio down sampling algorithm for color filter array (CFA) images. Color demosaiking is a necessary part of image signal processing pipeline for many types of digital image recording system using single sensor. Also, such as smart phone, obtained high resolution image from image sensor has to be down-sampled to be displayed on the screen. The conventional solution is "Demosaicking first and down sampling later". However, this scheme requires a significant amount of memory and computational cost. Also, artifacts can be introduced or details get damaged during demosaicking and down sampling process. In this paper, we propose a method in which demosaicking and down sampling are working simultaneously. We use inverse mapping of Bayer CFA and then joint demosaicking and down sampling with arbitrary-ratio scheme based on signal decomposition of high and low frequency component in input data. Experimental results show that our proposed algorithm has better image quality performance and much less computational cost than those of conventional solution.