• Journal of IKEEE
• /
• v.21 no.3
• /
• pp.284-287
• /
• 2017

In this study, we examined the simulated electrical characteristics of single-gated feedback field effect transistors (FBFETs) and the influence of channel length variation of the memory window characteristics through the 3D device simulation. The simulations were carried out for various channel lengths from 50 nm to 100 nm. The FBFETs exhibited zero SS(< 1 mV/dec) and a current $I_{on}/I_{off}$ ratio${\sim}1.27{\times}10^{10}$. In addition, the memory windows were 0.31 V for 50 nm-channel-length devices while no memory windows were observed for 100 nm-channel-length devices.

• ETRI Journal
• /
• v.10 no.3
• /
• pp.83-91
• /
• 1988

This paper describes the architecture and the performance analysis of a multiprocessor system, which is based on the shared memory and single system bus. The system bus provides the pended protocol for the multiprocessor environment. Analyzing the processor utilization, address/data bus utilization and memory conflicts, we use a simulation model. The hit ratio of private cache memory is a major factor on the linear increase of the performance of a shared memory based multiprocessor system.

• Journal of the Korean Operations Research and Management Science Society
• /
• v.39 no.4
• /
• pp.19-31
• /
• 2014

We study parallel processing techniques for the R programming language of high performance computing technology. In this study, we used massively parallel computing system which has 25,408 cpu cores. We conducted a performance evaluation of a distributed memory system using MPI and of a the shared memory system using OpenMP. Our findings are summarized as follows. First, For some particular algorithms, parallel processing is about 150 times faster than serial processing in R. Second, the distributed memory system gets faster as the number of nodes increases while shared memory system is limited in the improvement of performance, due to the limit of the number of cpus in a single system.

• Smart Structures and Systems
• /
• v.14 no.4
• /
• pp.541-558
• /
• 2014

This paper proposes a new design of shape memory alloy (SMA) wire actuated gripper for open mode operation. SMA can generate smooth muscle movements during actuation which make them potentially good contenders in designing grippers. The principle of the shape memory alloy gripper is to convert the linear displacement of the SMA wire actuator into the angular displacement of the gripping jaw. Steady state analysis is performed to design the wire diameter of the bias spring for a known SMA wire. The gripper is designed to open about an angle of $22.5^{\circ}$ when actuated using pulsating electric current from a constant current source. The safe operating power range of the gripper is determined and verified theoretically. Experimental evaluation for the uncontrolled gripper showed a rotation of $19.97^{\circ}$. Forced cooling techniques were employed to speed up the cooling process. The gripper is simple and robust in design (single movable jaw), easy to fabricate, low cost, and exhibits wide handling capabilities like longer object handling time and handling wide sizes of objects with minimum utilization of power since power is required only to grasp and release operations.

• Journal of Institute of Control, Robotics and Systems
• /
• v.20 no.4
• /
• pp.443-448
• /
• 2014

Soft errors in memory devices that caused by radiation are the main threat from a reliability point of view. This threat can be commonly overcome with the combination of SEC (Single-Error Correction) codes and scrubbing technique. The interleaving architecture can give memory devices the ability of tolerating these soft errors, especially against multiple-bit soft errors. And the interleaving distance plays a key role in building the tolerance against multiple-bit soft errors. This paper proposes a reliability model of an interleaved memory device which suffers from multiple-bit soft errors and are protected by a combination of SEC code and scrubbing. The proposed model shows how the interleaving distance works to improve the reliability and can be used to make a decision in determining optimal scrubbing technique to meet the demands in reliability.

• Information and Communications Magazine
• /
• v.25 no.12
• /
• pp.10-18
• /
• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.8
• /
• pp.111-121
• /
• 1994

This paper proposes a memory testable code called MTA(Memory TestAble) code which is based on error correcting code technique for testing functional faults in semiconductor memories. The characteristics of this code are analyzed and compared with those of conventional codes. The developed decoding technique for this code can reduce the decoder circuits up to 70% and obtain two-times faster decoding speed than other codes such as hamming code or Hsiao code. The MTA code is eccectively applicable to parallel testing of semiconductor memories because it has the same information length and parity length. It can detect from single error functional faults to triple error in semiconductor memories.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.14 no.2
• /
• pp.79-86
• /
• 2019

For decades, in-memory data structures have been designed for DRAM-based main memory that provides symmetric read/write performances and has no limited write endurance. However, such data structures provide sub-optimal performance for NVM as it has different characteristics to DRAM. With this motivation, we rethink a conventional red-black tree in terms of its efficacy under NVM settings. The original red-black tree constantly rebalances sub-trees so as to export fast access time over dataset, but it inevitably increases the write traffic, adversely affecting the performance for NVM with a long write latency and limited endurance. To resolve this problem, we present a variant of the red-black tree called a hierarchical balanced binary search tree. The proposed structure maintains multiple keys in a single node so as to amortize the rebalancing cost. The performance study reveals that the proposed hierarchical binary search tree effectively reduces the write traffic by effectively reaping the high capacity of NVM.

• Journal of KIISE
• /
• v.43 no.10
• /
• pp.1079-1084
• /
• 2016

Single-state parsing automata have a characteristic such that the decision of an action depends only on the current state but not on the parsing history. The memory space and the parsing time of single-state parsing automata are less than the memory space and the parsing time of LR automata. However, the applicable grammar class of single-state parsing automata is less than that of LR automata. This paper provides extended single-state parsing automata, which are applicable to LR grammars. In the prior work, the special state, referred to as the cyclic state was not treated in the construction of single-state parsing automata, and hence, the applicable grammar class was less than LR grammars. The paper solves the problem of cyclic states by processing dynamic information depending on an input string. The proposed method expands the application of grammar class of single-state parsing automata to LR grammars.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.3
• /
• pp.61-71
• /
• 2014

As the occupancy rate of the flash memory increases in the storage media market for the embedded system and the semi-conductor industry grows, the demand and supply of flash memory is increasing by a big margin. They are especially used in large quantity in the smart phones, tablets, PC, SSD and Soc(System on Chip) etc. The flash memory is divided into the NOR type and NAND type according to the cell arrangement structure and the NAND type is divided into the SLC(Single Level Cell) and MLC(Multi Level Cell) according to the number of bits that can be stored in each cell. Many tests have been performed on NOR type such as BIST(Bulit-In Self Test) and BIRA(Bulit-In Redundancy Analysis) etc, but there is little study on the NAND type. For the case of the existing BIST, the test can be proceeded using external equipments like ATE of high price. However, this paper is an attempt for the improvement of credibility and harvest rate of the system by proposing the BIST for the MLC NAND type flash memory of Finite State Machine structure on which the pattern test can be performed without external equipment since the necessary patterns are embedded in the interior and which uses the MLC NAND March(x) algorithm and pattern which had been proposed for the MLC NAND type flash memory.