• Journal of IKEEE
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• v.26 no.1
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• pp.43-49
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• 2022

This paper compares the sensorless control performance according to the applied voltage waveform by injecting sinusoidal, triangular, and square waveform in the harmonic injection sensorless control method. By injecting various voltage shape waveform with a frequency of 1kHz, the error amount of the estimated angle for each waveform is compared and analyzed. For the experiment, the HILS(hardware in the loop simulation) system was used. The hardware is the control board, and the inverter and motor models implemented in Simulik are located in the real-time simulator. The control algorithm is implemented by the FPGA control board, which includes a PWM interrupt service routine with a frequency of 10 kHz, harmonic injection and position detection sensorless algorithm.

• The Journal of Korean Physical Therapy
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• v.36 no.1
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• pp.39-44
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• 2024

Purpose: Cybersickness is a type of motion sickness induced by virtual reality (VR) or augmented reality (AR) environments that presents symptoms including nausea, dizziness, and headaches. This study aimed to investigate how cathodal transcranial direct current stimulation (tDCS) alleviates motion sickness symptoms and modulates brain activity in individuals experiencing cybersickness after exposure to a VR environment. Methods: This study was performed on two groups of healthy adults with cybersickness symptoms. Subjects were randomly assigned to receive either cathodal tDCS intervention or sham tDCS intervention. Brain activity during VR stimulation was measured by 38-channel functional near-infrared spectroscopy (fNIRS). tDCS was administered to the right temporoparietal junction (TPJ) for 20 minutes at an intensity of 2mA, and the severity of cybersickness was assessed pre- and post-intervention using a simulator sickness questionnaire (SSQ). Result: Following the experiment, cybersickness symptoms in subjects who received cathodal tDCS intervention were reduced based on SSQ scores, whereas those who received sham tDCS showed no significant change. fNIRS analysis revealed that tDCS significantly diminished cortical activity in subjects with high activity in temporal and parietal lobes, whereas high cortical activity was maintained in these regions after intervention in subjects who received sham tDCS. Conclusion: These findings suggest that cathodal tDCS applied to the right TPJ region in young adults experiencing cybersickness effectively reduces motion sickness induced by VR environments.

• Journal of the Ergonomics Society of Korea
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• v.34 no.3
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• pp.247-264
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• 2015

Objective: The purpose of this study is to determine the priority of information presentation and the effective menu type to be placed in the center of a gauge cluster display for commercial trucks and to present a set of ergonomic designs for the gauge cluster display. Background: An effective ergonomic design is specifically needed for the development of the gauge cluster display for the commercial trucks, because more diverse and heavier information is delivered to truck drivers, compared to the information to passenger car drivers. Method: First, all the information that must be shown on the commercial truck display was collected. Then, the severity, frequency of use, and display design parameters were evaluated for those information by commercial truck drivers. Next, an analysis on the information attributes and the heuristic evaluation utilizing the display design principles were carried out. According to the results, a design alternative of the main screen to be displayed was constructed by priority. A comparative analysis between the alternative and existing main screens was also conducted to see the efficacy of the designs. Lastly, we conducted an experiment for the selection of menu type. The experiment was conducted using the driving simulator with an eye-tracking device. The independent variables were four types of the menu reflecting the commercial truck characteristics such as grid type, icon type, list type, and flow type. We measured preference, total execution time, the total duration of fixation on the gauge cluster area, and the total number of fixation on the gauge cluster area as dependent variables. Results: Four types of driver convenience information and six types of driver assistance information were selected as the information to be placed primarily on the main screen of the gauge cluster. The Grid type was the most effective among the menu types. Conclusion: In this study, the information that appears on the main screen of the display, the division of the display and the design of the menu type for commercial truck drivers were suggested. Application: This study is expected to be utilized as guidelines on the ergonomic design of a gauge cluster display for commercial trucks.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.21 no.5
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• pp.15-27
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• 2022

An omnidirectional VR treadmill is a highly-immersive walking simulator that allows identical body movements, such as walking, running, and sitting. However, the operation difficulty of an omnidirectional VR treadmill may cause data reliability problems. Therefore, this study aims to verify the effectiveness of a VR treadmill by comparing the ability to orient in the real and virtual worlds spatially. For this purpose, a rotating and searching path experiment was conducted with participants. This experiment showed that there was no statistically significant difference in the ability of the participants to orient in the real and virtual worlds spatially. In addition, the omnidirectional VR treadmill requires an adaptation time for the users due to the difficulty in the treadmill operation. However, there was no significant difference in the difficulty felt by the participants according to the adaptation time. Hence, these findings supported the possibility of collecting realistic walking data without safety concerns through an omnidirectional VR treadmill. Furthermore, this treadmill could be used in future research to solve problems directly related to pedestrian safety, such as the interaction between vehicles and pedestrians.

• Journal of Internet Computing and Services
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• v.16 no.4
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• pp.61-70
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• 2015

This paper presents a web-based Java applet for understanding the concepts in digital logic circuits and student satisfaction survey was carried out in order to show its educational validity. Through our educational Java applet, the learners will be capable of learning the concepts and principles related to digital logic circuit experiments and how to operate virtual experimental equipments and virtual bread board. The proposed educational Java applet is composed of five important components: Principle Classroom to explain the concepts and principles for digital logic circuit operations, Simulation Classroom to provide a web-based simulator to the learners, Virtual Experiment Classroom to provide interactive Java applet about the syllabus of off-line laboratory class, Assessment Classroom, and Management System. With the aid of the Management System every classroom is organically tied together collaborating to achieve maximum learning efficiency. Finally, we have obtained several affirmative effects such as high learning standard, reducing the total experimental hours and the damage rate for experimental equipments.

• Journal of the Korea Society for Simulation
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• v.27 no.2
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• pp.35-48
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• 2018

The study of air defense against North Korean tactical ballistic missiles (TBM) should consider the rapidly changing battlefield environment. The study for target re-designation for intercept missiles enables effective operation of friendly defensive assets as well as responses to dynamic battlefield. The researches that have been conducted so far do not represent real-time dynamic battlefield situation because the hit probability for the TBM, which plays an important role in the decision making process, is fixed. Therefore, this study proposes a target re-designation algorithm that makes decision based on hit probability which considers real-time field environment. The proposed method contains a trajectory prediction model that predicts the expected trajectory of the TBM from the current position and velocity information by using random forest and moving window. The predicted hit probability can be calculated through the trajectory prediction model and the simulator of the intercept missile, and the calculated hit probability becomes the decision criterion of the target re-designation algorithm for the missile. In the experiment, the validity of the methodology used in the TBM trajectory prediction model was verified and the superiority of using the hit probability through the proposed model in the target re-designation decision making process was validated.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.4
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• pp.193-205
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• 2003

There has been so many research activities about robot soccer system in the many research fields, for example, intelligent control, communication, computer technology, sensor technology, image processing, mechatronics. Especially researchers research strategy for attacking in the field of strategy, and develop intelligent strategy. Then, soccer robots cannot defense completely and efficiently by using simple defense strategy. Therefore, intention extraction of attacker is needed for efficient defense. In this thesis, intention extractor of soccer robots is designed and developed based on FMMNN(Fuzzy Min-Max Neural networks ). First, intention for soccer robot system is defined, and intention extraction for soccer robot system is explained.. Next, FMMNN based intention extractor for soccer robot system is determined. FMMNN is one of the pattern classification method and have several advantages: on-line adaptation, short training time, soft decision. Therefore, FMMNN is suitable for soccer robot system having dynamic environment. Observer extracts attack intention of opponents by using this intention exactor, and this intention extractor is also used for analyzing strategy of opponent team. The capability of developed intention extractor is verified by simulation of 3 vs. 3 robot succor simulator. It was confirmed that the rates of intention extraction each experiment increase.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.1
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• pp.139-145
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• 2016

Dumbbell is the most basic topology that can be used in almost all kind of network experiment within it or just by little expansion. While Transmission Control Protocol TCP is the basic protocol that is used for the connectivity among networks and stations. TCP major and basic goal is to provide path and services to different applications for communication. For that reason TCP has to transfer a lot of data through a communication medium that cause serious congestion problem. To calculate the congestion problem, different kind of pre-cure solutions are developer which are Loss Based Variant and Delay Based Variant. While LBV keep track of the data that is going to be passed through TCP protocol, if the data packets start dropping that means congestion occurrence which notify as a symptom, TCP CUBIC use LBV for notifying the loss. Similarly the DBV work with the acknowledgment procedure that is used in when data ACK get late with respect to its set data rate time, TCP COMPOUND/VAGAS are examples of DBV. Many algorithms have been purposed to control the congestion in different TCP variants but the loss of data packets did not completely controlled. In this paper, the congestion control algorithms are implemented and corresponding results are analyzed in Dumbbell topology, it is typically used to analyze the TCP traffic flows. Fairness of throughput is evaluated for different TCP variants using network simulator (NS-2).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.20-27
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• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.116-126
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• 2011

In this paper, we present a multi-media processor which can decode multiple-format video standards. The designed processor is evaluated with optimized MPEG-2, MPEG-4, and AVS (Audio video standard). There are two approaches for developing of real-time video decoders. First, hardware-based system is much superior to a processor-based one in execution time. However, it takes long time to implement and modify hardware systems. On the contrary, the software-based video codecs can be easily implemented and flexible, however, their performance is not so good for real-time applications. In this paper, in order to exploit benefits related to two approaches, we designed a processor called ASIP(Application specific instruction-set processor) for video decoding. In our work, we extracted eight common modules from various video decoders, and added several multimedia instructions to the processor. The developed processor for video decoders is evaluated with the Synopsys platform simulator and a FPGA board. In our experiment, we can achieve about 37% time saving in total decoding time.