• Journal of Korea Multimedia Society
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• v.8 no.12
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• pp.1605-1612
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• 2005

This paper presents the knowledge and experience we obtained by employing multiprocessor systems as a computer simulation design verification to study high-performance computing system. This paper also describes a case study of symmetric multiprocessors (SMP) kernel on a 32 CPUs CC-NUMA architecture using an actual architecture. A small group of CPUs of CC-NUMA, high-performance computer system, is clustered into a processing node or cluster. By simulating the system design verification tools; we discussed SMP OS kernel on a CC-NUMA multiprocessor architecture performance which is $32\%$ of the total execution time and remote memory access latency is occupied $43\%$ of the OS time. In this paper, we demonstrated our simulation results for multiprocessor, high-performance computing system performance, using simulation-based design verification.

• The Magazine of the IEIE
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• v.30 no.9
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• pp.1002-1011
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• 2003

In this paper, we introduce an integrated SoC front-end design & verification environment which can be practically used in the embedded 32-bit processor-core SoC VLSI design. Our introduced SoC design & verification environment integrates two most important flows, such as the RTL power estimation and code coverage analysis, with the functional verification (chip validation) flow which is used in the conventional simulation-based design. For this, we developed two simulation-based inhouse tools, RTL power estimator and code coverage analyzer, and used them to adopt them to our RTL design and to increase the design quality of that. Our integrated design environment also includes basic design and verification flows such as the gate-level functional verification with back annotation information and test vector capture & replay environment.

• Journal of Ocean Engineering and Technology
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• v.27 no.1
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• pp.24-30
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• 2013

The Korea Navy has been making constant efforts to apply M&S (modeling and simulation) to naval ship development, and the generalization of M&S for ship development is a trend. M&S for ship design is used for the V&V (verification and validation) of its design and operation, including design verification and ergonomic design that considers the crew using the Naval Ship Product Model. In addition, many parts of this M&S are repeatedly accomplished regardless of the kinds of ships. This study aims to standardize M&S, which repeatedly applies similar verifications for operation scenarios. A congestion assessment simulation for the major spaces of ships was the subject of the standardization based on the leading research results of various researchers, and a simulation automation solution was suggested. An information model using XML was proposed through the simulation automation concept, and a prototype system based on it was implemented. The usability was shown through a case study that verified the operability performance of the crew messroom.

• International Journal of Aeronautical and Space Sciences
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• v.18 no.3
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• pp.574-578
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• 2017

In order to achieve iterative design in early R&D period, a Distributed and Real-time Integrated Simulation System for avionics based on a Model-Based Systems Engineering (MBSE) method is proposed. The proposed simulation system includes driver, simulation model, monitor, flight visual model and aircraft external model.The effect of this simulation system in iterative design and system verification is testified by several use cases. The result shows that the simulation system, which can play an important role in iterative design and system verification, can reduce project costs and shorten the entire R&D period.

• Smart Media Journal
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• v.1 no.1
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• pp.48-52
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• 2012

A reliable test of offshore plant hold a key post in offshore engineering technology. The offshore self-supporting of process module design and basic design technology needs engineering verification based on the reliable test. And also reliable verification test data is very important. Therefore, verification test system for offshore installation simulation is necessary. This paper explains design of data acquisition system and control system based on the parameter of measured and controlled variable which is for establishing offshore installation simulation system.

• Journal of the Semiconductor & Display Technology
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• v.23 no.1
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• pp.25-35
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• 2024

In the present modern day, as the complexity and size of SoC(System on Chip) increase, the importance of design verification are increasing, Therefore it takes a lot of time to verify the design. There is an emerging need to manage the verification environment faster and more efficiently by reusing the existing verification environment. UVM-based verification is a standardized and highly reliable verification method widely adopted and used in the semiconductor industry. This paper presents a UVM-based verification for the 4 tap equalizer module with a systolic array structure. Through the constraints randomization, it was confirmed that various test scenarios stimulus were generated. In addition, by verifying a simulation comparing the actual DUT outputs with the MATLAB reference outputs, the reuse and efficiency of the UVM test bench could be confirmed.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.167-170
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• 2003

In this paper, a design and experiment of PCI Express Core verification Model is described. The model targeting Endpoint core verification is designed by using newly-emerging SystemC which is a system design language based on a new C++ class library and simulation engine. In the verification model, we developed a SystemC Host System model which act as a Root Complex and Device Driver dedicated to the PCI Express Endpoint RTL Core. The test of Host System Model is guided by scenarios which implements and acts point of Device Driver and Root Complex and shows the result of simulation. Also, We present the full structure of verification model and Host model.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.141-146
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• 2007

In this paper, we proposed an efficient FPGA-based simulation acceleration method based on FPGA compilation avoidance, which can effectively decrease the long debugging turnaround time incurred from the every debugging process in the functional verification. The proposed method had been experimentally applied to the functional verification for a microcontroller design. It had clearly shown that the debugging turnaround time was greatly reduced while the high simulation speed of the simulation acceleration was still maintained.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.755-758
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• 1998

As the performance of microprocessor improves, the design complexity grows exponentially. Therefor, it is very important to make the bug-free model as early as possible in a design life-cycle. This paper describes the simulation-based functional verification methodology for the RTL level description model. It is performed by multi-stage verification methods using extensive hand-generated self-checking tests supplemented with random tests. This approach is opplied to the functional verification of the GPU processor of Raptor and various bugs are detected.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.3
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• pp.261-267
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• 2002

In SOC(System On a Chip) designs, reducing time and cast for design verification is the most critical to improve the design productivity. this is mainly because the designs require co-verifying HW together with SW, which results in the increase of verification complexity drastically. In this paper, to cope with the verification crisis in SOC designs, we propose a new verification methodology, so called integrated co-verification, which lightly combine both co-simulation and co-emulation in unified and seamless way. We have applied our integrated co-verification to ARM/AMBA platform-based co-verification environment with a commercial co-verification tool, Seamless CVE, and a physical prototyping board. The experiments has shown clear advantage of the proposed technique over conventional ones.