• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.939-942
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• 2003

Design verification problem is emerging as an important issue to detect any design errors at the early stage of the design. Conventionally, design verifications have been done using a simulation technique. However, this technique has been proved not to cover all potential design errors. Therefore, formal technique is often used to verify digital circuits as an alternative. In this paper we adopted formal verification technique and verified some important properties derived from our pipelined digital systems, using SMV (Symbolic Model Verifier). Our example shows that model checking method (one of formal verification techniques) can be effectively performed in verifying the large digital systems.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권2호
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• pp.132-140
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• 2002

This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

• 반도체디스플레이기술학회지
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• 제23권1호
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• pp.25-35
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• 2024

In the present modern day, as the complexity and size of SoC(System on Chip) increase, the importance of design verification are increasing, Therefore it takes a lot of time to verify the design. There is an emerging need to manage the verification environment faster and more efficiently by reusing the existing verification environment. UVM-based verification is a standardized and highly reliable verification method widely adopted and used in the semiconductor industry. This paper presents a UVM-based verification for the 4 tap equalizer module with a systolic array structure. Through the constraints randomization, it was confirmed that various test scenarios stimulus were generated. In addition, by verifying a simulation comparing the actual DUT outputs with the MATLAB reference outputs, the reuse and efficiency of the UVM test bench could be confirmed.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 2000년도 추계학술대회 논문집
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• pp.11-15
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• 2000

• 대한설비공학회:학술대회논문집
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• 대한설비공학회 2009년도 하계학술발표대회 논문집
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• pp.745-750
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• 2009

In Korea, since the implementation of the GMO Law, the intrest of biosafety level 3(BL3) lab. is increasing. In this study, using CONTAM which is applying multizone modelling, the multizone simulation for design verification of BL3 lab. was performed. In BL3 lab., because required air change rate is greater than general estimated air-conditioning load and it is difficult to maintain room pressure difference efficiently, to maintain pressure difference between laboratory rooms is important through sealing condition of doors and proper airflow control of laboratory rooms. In this study, about BL3 lab.(M. tuberculosis research lab.), the multizone simulation for four kind of biohazard scenarios was performed in the case of unexpected spread of contaminants in the laboratory room, anteroom, corridor and inside of BSC. Multizone simulation results show that these approach methods are used as a tool for the design and verification of BL3 lab.

• 설비공학논문집
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• 제21권12호
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• pp.671-677
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• 2009

In Korea, since the implementation of the LMO Law, the interest of biosafety level 3(BL3) lab. is increasing. In this study, using CONTAM which is applying multizone modelling, the multizone simulation for design verification of BL3 lab. is performed. In BL3 lab., because required air change rate is greater than general estimated air-conditioning load and it is difficult to maintain room pressure difference efficiently, to maintain pressure difference between laboratory rooms is important through sealing condition of doors and proper airflow control of laboratory rooms. In this study, about BL3 lab,(M. tuberculosis research lab.), the multizone simulation for four kind of biohazard scenarios is carried out in the case of unexpected spread of contaminants in the laboratory room, anteroom, corridor and inside of BSC. Multizone simulation results show that these approach methods are used as a tool for the design and verification of BL3 lab.

• 한국시뮬레이션학회논문지
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• 제27권3호
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• pp.23-36
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• 2018

이산사건시스템명세(DEVS) 형식론은 이산사건시스템을 모듈러하고 계층적으로 모델링할 수 있는 잘 정의된 의미론을 제공하고 있어 이산사건시스템 모델링 시뮬레이션 (M&S)에 많이 사용되어 왔다. 이러한 수학적 표현 대신에 DEVS 다이어그램은 복잡한 시스템을 보다 직관적이며 편리한 표현력을 제공한다. 본 논문은 DEVS 다이어그램을 이용하여 표현된 모델을 시뮬레이션 코드로 체계적으로 구현하며 검증하는 DEVS 클린룸 프로세스를 제안하였다. 구체적으로, 주어진 다이어그램 모델의 적합성 검사, 테이블 DEVS 모델로의 변환, 마지막으로 시뮬레이션 소스코드로 변환하는 방법과 역으로 추적성을 기반으로 한 검사기법을 통해 정적 검증하는 구체적인 방법을 제시하였다. 간단한 예제를 통해 제안된 프로세스를 적용하는 구체적인 방법을 설명하였으며, 적용사례 통해 제안된 기법이 실용적으로 적용 가능한 효과적인 프로세스임을 확인하였다.

• 전자공학회논문지A
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• 제33A권5호
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• pp.180-187
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• 1996

This paper describes a post-layout simulation method using VHDL and C for verifying the architecture of antifuse-based FPGAs and the dedicated CAD system. An antifuse-based FPGA consists of programming circuitry including decoding logic, logic modules, segmented tracks, antifuses and I/O pads. The VHDL model which includes all these elements is used for logic verification and programming verification of the implemented circuit by reconstructing the logic circuit from the bit-stream generated from layout tool. The implemented circuit comprises of logic modules and routing networks. Since the routing delay of the complex networks is comparable to the delay of the logic module in the FPGA, the accurate post-layout simulation is essential to the FPGA system. In this paper, the C program calculates the delay of the routing netowrks using SPICE, elmore or horowitz delay models and the results feedback to the VHDL simulation. Critical path anc be found from this post-layout simulation results.

• 전기학회논문지
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• 제56권12호
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• pp.2091-2097
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• 2007

This paper described the verification of modeling technique of underground distribution from comparison between field test and simulation. It needs more exact transient phenomenon analysis model to establish lightning protection of underground distribution line. Although, there were a lot of transient phenomenon researches, nobody could has verified the confidence of modeling from field tests in interior until now. So, simulation model verified field test is needed to analyse transient phenomenon of underground distribution system. The examination must be accomplished in many different condition before suggesting these verified analysis model. In this paper, the conditions were examined and the various data results on the different line composition was compared with the EMTP simulation, when the lightning impulse test was accomplished at underground distribution line. Also the value between field test and simulation was very closed and the method of modeling has demonstrated confidence, when the method is used to analyse domestic transient phenomenon of underground distribution.

• Nuclear Engineering and Technology
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• 제53권5호
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• pp.1664-1675
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• 2021

In order to verify the statistical performance of the nonparametric tests used in the MARSSIM approach, all plausible contamination distribution types that can be encountered in a survey area should be investigated. As the first of such investigations, this study aims to perform the verification for normal distribution of the contamination in a survey area by simulating the collection of random samples from it through the Monte Carlo simulation. The results of the simulations conducted for a total of 81 simulation cases showed that Sign test and WRS test both exhibited an excellent statistical performance: 100% for the former and 98.8% for the latter. Therefore, in final status surveys of the MARSSIM approach, a high statistical performance can be expected in applying the nonparametric hypothesis tests to survey areas whose net contamination can be assumed to be normally distributed.