• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.215-216
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• 2013

The silicide is a compound of Si with an electropositive component. Silicides are commonly used in silicon-based microelectronics to reduce resistivity of gate and local interconnect metallization. The popular silicide candidates, CoSi2 and TiSi2, have some limitations. TiSi2 showed line width dependent sheet resistance and has difficulty in transformation of the C49 phase to the low resistive C54. CoSi2 consumes more Si than TiSi2. Nickel silicide is a promising material to substitute for those silicide materials providing several advantages; low resistivity, lower Si consumption and lower formation temperature. Nickel silicide (NiSi) nanowire (NW) has features of a geometrically tiny size in terms of diameter and significantly long directional length, with an excellent electrical conductivity. According to these advantages, NiSi NWs have been applied to various nanoscale applications, such as interconnects [1,2], field emitters [3], and functional microscopy tips [4]. Beside its tiny geometric feature, NW can provide a large surface area at a fixed volume. This makes the material viable for photovoltaic architecture, allowing it to be used to enhance the light-active region [5]. Additionally, a recent report has suggested that an effective antireflection coating-layer can be made with by NiSi NW arrays [6]. A unique growth mechanism of nickel silicide (NiSi) nanowires (NWs) was thermodynamically investigated. The reaction between Ni and Si primarily determines NiSi phases according to the deposition condition. Optimum growth conditions were found at $375^{\circ}C$ leading long and high-density NiSi NWs. The ignition of NiSi NWs is determined by the grain size due to the nucleation limited silicide reaction. A successive Ni diffusion through a silicide layer was traced from a NW grown sample. Otherwise Ni-rich or Si-rich phase induces a film type growth. This work demonstrates specific existence of NiSi NW growth [7].

• Current Photovoltaic Research
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• v.4 no.3
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• pp.124-129
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• 2016

Recently industry has voiced a need for optimally designing the production process of low-cost, high-quality ingots by improving productivity and reducing production costs with the Czochralski process. Crystalline defect control is important for the production of high-quality ingots. Also oxygen is one of the most important impurities that influence crystalline defects in single crystals. Oxygen is dissolved into the silicon melt from the silica crucible and incorporated into the crystalline a far larger amount than other additives or impurities. Then it is eluted during the cooling process, there by causing various defect. Excessive quantities of oxygen degrade the quality of silicone. However an appropriate amount of oxygen can be beneficial. because it eliminates metallic impurities within the silicone. Therefore, when growing crystals, an attempt should be made not to eliminate oxygen, but to uniformly maintain its concentration. Thus, the control of oxygen concentration is essential for crystalline growth. At present, the control of oxygen concentration is actively being studied based on the interdependence of various factors such as crystal rotation, crucible rotation, argon flow, pressure, magnet position and magnetic strength. However for methods using a magnetic field, the initial investment and operating costs of the equipment affect the wafer pricing. Hence in this study simulations were performed with the purpose of producing low-cost, high-quality ingots through the development of a process to optimize oxygen concentration without the use of magnets and through the following. a process appropriate to the defect-free range was determined by regulating the pulling rate of the crystals.

• Bulletin of the Korean Space Science Society
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• 2008.10a
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• pp.33.3-34
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• 2008

As an activity of building Korean Space Weather Prediction Center (KSWPC), we has studied of radiation effect on the spacecraft components. High energy charged particles trapped by geomagnetic field in the region named Van Allen Belt can move to low altitude along magnetic field and threaten even low altitude spacecraft. Space Radiation can cause equipment failures and on occasions can even destroy operations of satellites in orbit. Sun sensors aboard Science and Technology Satellite (STSAT-1) was designed to detect sun light with silicon solar cells which performance was degraded during satellite operation. In this study, we try to identify which particle contribute to the solar cell degradation with ground based radiation facilities. We measured the short circuit current after bombarding electrons and protons on the solar cells same as STSAT-1 sun sensors. Also we estimated particle flux on the STSAT-1 orbit with analyzing NOAA POES particle data. Our result clearly shows STSAT-1 solar cell degradation was caused by energetic protons which energy is about 700 keV to 1.5 MeV. Our result can be applied to estimate solar cell conditions of other satellites.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.5
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• pp.1143-1150
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• 2000

A dual-mode multiplier (DMM) that performs single- and double-precision multiplications has been designed using a $0.25-\mum$ 5-metal CMOS technology. An algorithm for efficiently implementing double-precision multiplication with a single-precision multiplier was proposed, which is based on partitioning double-precision multiplication into four single-precision sub-multiplications and computing them with sequential accumulations. When compared with conventional double-precision multipliers, our approach reduces the hardware complexity by about one third resulting in small silicon area and low-power dissipation at the expense of increased latency and throughput cycles. The DMM consists of a $28-b\times28-b$ single-precision multiplier designed using radix-4 Booth receding and redundant binary (RB) arithmetic, an accumulator and a simple control logic for mode selection. It contains about 25,000 transistors on the area of about $0.77\times0.40-m^2$. The HSPICE simulation results show that the DMM core can safely operate with 200-MHZ clock at 2.5-V, and its estimated power dissipation is about 130-㎽ at double-precision mode.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.239-244
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• 1998

Piezoelectric pressure sensors and pyroelectric infrared detectors based on ZnO thin film have been integrated with GaAs metal-semiconductor field effect transistor (MESFET) amplifiers. Surface micromachining techniques have been applied in a GaAs MESFET process to form both microsensors and electronic circuits. The on-chip integration of microsensors such as pressure sensors and infrared detectors with GaAs integrated circuits is attractive because of the higher operating temperature up to 200 oC for GaAs devices compared to 125 oC for silicon devices and radiation hardness for infrared imaging applications. The microsensors incorporate a 1${\mu}$m-thick sputtered ZnO capacitor supported by a 2${\mu}$m-thick aluminum membrane formed on a semi-insulating GaAs substrate. The piezoelectric pressure sensor of an area 80${\times}$80 ${\mu}$m2 designed for use as a miniature microphone exhibits 2.99${\mu}$V/${\mu}$ bar sensitivity at 400Hz. The voltage responsivity and the detectivity of a single infrared detector of an area 80${\times}$80 $\mu\textrm{m}$2 is 700 V/W and 6${\times}$108cm$.$ Hz/W at 10Hz respectively, and the time constant of the sensor with the amplifying circuit is 53 ms. Circuits using 4${\mu}$m-gate GaAs MESFETs are fabricated in planar, direct ion-implanted process. The measured transconductance of a 4${\mu}$m-gate GaAs MESFET is 25.6 mS/mm and 12.4 mS/mm at 27 oC and 200oC, respectively. A differential amplifier whose voltage gain in 33.7 dB using 4${\mu}$m gate GaAs MESFETs is fabricated for high selectivity to the physical variable being sensed.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.3.1-3.1
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• 2011

Over the past decade, the major efforts for lowering the cost of electronics has been devoted to increasing the packaging efficiency of the integrated circuits (ICs), which is defined by the ratio of all devices on system-level board compared to the area of the board, and to working on a larger but cheaper substrates. Especially, in flexible electronics, the latter has been the favorable way along with using novel nanomaterials that have excellent mechanical flexibility and electrical properties as active channel materials and conductive films. Here, the tool for achieving large area patterning is by printing methods. Although diverse printing methods have been investigated to produce highly-aligned structures of the nanomaterials with desired patterns, many require laborious processes that need to be further optimized for practical applications, showing a clear limit to the design of the nanomaterial patterns in a large scale assembly. Here, we demonstrate the alignment of highly ordered and dense silicon (Si) NW arrays to anisotropically etched micro-engraved structures using a simple evaporation process. During evaporation, entropic attraction combined with the internal flow of the NW solution induced the alignment of NWs at the corners of pre-defined structures. The assembly characteristics of the NWs were highly dependent on the polarity of the NW solutions. After complete evaporation, the aligned NW arrays were subsequently transferred onto a flexible substrate with 95% selectivity using a direct gravure printing technique. As proof-of-concept, flexible back-gated NW field effect transistors (FETs) were fabricated. The fabricated FETs had an effective hole mobility of 0.17 $cm2/V{\cdot}s$ and an on/off ratio of ${\sim}1.4{\times}104$. These results demonstrate that our NW gravure printing technique is a simple and effective method that can be used to fabricate high-performance flexible electronics based on inorganic materials.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.79-84
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• 2006

This paper proposed a novel H.264 deblocking filter for low-power mobile multimedia SoCs. In H.264 deblocking filter, filtering can be skipped on some pixels when pixel value differences satisfy some specific conditions. Furthermore, whole filtering can be skipped when quantization parameter is less than 16. Based on these features, power consumption can be significantly reduced by shutting down deblocking filter partially or as a whole. The proposed deblocking filter can shut down partial or whole blocks with simple control circuits. Common hardware performs both horizontal filtering and vertical filtering. It was implemented in silicon chip using $0.35{\mu}m$ standard cell library technology. The gate count is about 20,000 gates. The maximum operation frequency is 108MHz. The maximum throughput is 30 frame/s with CCIR601 image format.

• Journal of the Korea Institute of Military Science and Technology
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• v.1 no.1
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• pp.227-237
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• 1998

HgCdTe Is the most versatile material for the developing infrared devices. Not like III-V compound semiconductors or silicon-based photo-detecting materials, HgCdTe has unique characteristics such as adjustable bandgap, very high electron mobility, and large difference between electron and hole mobilities. Many research groups have been interested in this material since early 70's, but mainly due to its thermodynamic difficulties for preparing materials, no single growth technique is appreciated as a standard growth technique in this research field. Solid state recrystallization(SSR), travelling heater method(THM), and Bridgman growth are major techniques used to grow bulk HgCdTe material. Materials with high quality and purity can be grown using these bulk growth techniques, however, due to the large separation between solidus and liquidus line on the phase diagram, it is very difficult to grow large materials with minimun defects. Various epitaxial growth techniques were adopted to get large area HgCdTe and among them liquid phase epitaxy(LPE), metal organic chemical vapor deposition(MOCVD), and molecular beam epitaxy(MBE) are most frequently used techniques. There are also various types of photo-detectors utilizing HgCdTe materials, and photovoltaic and photoconductive devices are most interested types of detectors up to these days. For the larger may detectors, photovoltaic devices have some advantages over power-requiring photoconductive devices. In this paper we reported the main results on the HgCdTe growing and characterization including LPE and MOCVD, device fabrication and its characteristics such as single element and linear array($8{\times}1$ PC, $128{\times}1$ PV and 4120{\times}1$ PC). Also we included the results of the dewar manufacturing, assembling, and optical and environmental test of the detectors.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1999.06a
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• pp.187-207
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• 1999

The thermal distributions near the growth interface of 150mm CZ crystals were measured by three thermocouples installed at the center, middle (half radius) and edge (10m from surface) of the crystals. The results show that larger growth rates produced smaller thermal gradients. This contradicts the widely used heat flux balance equation. Using this fact, it si confirmed in CZ crystals that the type of point defects created is determined by the value of the thermal gradient (G) near the interface during growth, as already reported for FZ crystals. Although depending on the growth systems the effective lengths of the thermal gradient for defect generation are varied, were defined the effective length as 10mm from the interface in this experiment. If the G is roughly smaller than 20C/cm, vacancy rich CZ crystals are produced. If G is larger than 25C/cm, the species of point defects changes dramatically from vacancies to interstitial. The experimental results which FZ and CZ crystals are detached from the melt show that growth interfaces are filled with vacancy. We propose that large G produces shrunk lattice spacing and in order to relax such lattice excess interstitial are necessary. Such interstitial recombine with vacancies which were generated at the growth interface, next occupy interstitial sites and residuals aggregate themselves to make stacking faults and dislocation loops during cooling. The shape of the growth interface is also determined by the distributions of G across the interface. That is, the small G and the large G in the center induce concave and convex interfaces to the melt, respectively.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.6 no.2
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• pp.185-193
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• 1996

$2.5^{\circ}\;and\;5^{\circ}$ tilted (100) Si wafer were oxidized in dry oxygen, and the differences in thermal oxidation behavior and oxidation induced stacking faults (OSF) between specimens were investigated. Ellipsometer measurements of the oxide thickness produced by oxidation in dry oxygen from 900 to $1200^{\circ}C$ showed that the oxidation rates of the tilted (100) Si were more rapid than those of the (100) Si and the differences between them decreased as the oxidation temperature increased. The activation energies based on the parabolic rate constant, B for (100) Si, $2.5^{\circ}$ off (100) Si and $5^{\circ}$ off (100) Si were 27.3, 25.9, 27.6 kcal/mol and those on the linear rate constant, B/A were 58.6, 56.6, 57.6 kcal/mol, respectively. Also, considerable decrease in the density of oxidation induced stacking faults for the $5^{\circ}$ off (100) Si was observed through optical microscopy after preferentially etching off the oxide layer, and the angle of stacking faults were changed with tilted angles.