• 제목/요약/키워드: Silicon vapor

검색결과 670건 처리시간 0.029초

HCL가스에 의한 실리콘 기판의 에칭 (Vapor Etching of Silicon Substrates with HCL Gas)

  • 조경익;윤동한;송성해
    • 대한전자공학회논문지
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    • 제21권5호
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    • pp.41-45
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    • 1984
  • 양질의 에피택셜 층을 성장시키기 위해서는, 에피택셜 층을 성장시키기 직전에 HCl 가스를 사용하여 실리콘 기판을 에칭하는 과정이 거의 언제나 포함된다. 본 논문에서는, 대기압[1 기압]과 감압[0.1기압]에서 HCl 가스 농도와 에칭 온도의 변화에 따른 에칭속도 및 에치-피트 생성에 관하여 조사하였다. 그 결과, 대기압 공정과 감압 공정 모두 에칭 속도는 HCI 가스 농도의 2승[X ]에 비례하였으며, 명목상 활성화 에너지는 0∼11 Kcal/mole인 것으로 나타났다. 이러한 결과로부터, 감압 공정에서 HCl 가스에 의해 실리콘이 에칭되는 것은 대기압 공정에서와 같이 다음과 같은 반응에 의해 일어난다고 예측된다; Si + 2HCl ↔SiCl2 + H2.

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절연체위의 다결정실리콘 재결정화 공정최적화와 그 전기적 특성 연구 (Optical process of polysilicaon on insulator and its electrical characteristics)

  • 윤석범;오환술
    • E2M - 전기 전자와 첨단 소재
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    • 제7권4호
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    • pp.331-340
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    • 1994
  • Polysilicon on insulator has been recrystallized by zone melting recrystallization method with graphite strip heaters. Experiments are performed with non-seed SOI structures. When the capping layer thickness of Si$\_$3/N$\_$4//SiO$\_$2/ is 2.0.mu.m, grain boundaries are about 120.mu.m spacing and protrusions reduced. After the seed SOI films are annealed at 1100.deg. C in NH$\_$3/ ambient for 3 hours, the recrystallized silicon surface has convex shape. After ZMR process, the tensile stress is 2.49*10$\^$9/dyn/cm$\^$2/ and 3.74*10$\^$9/dyn/cm$\^$2/ in the seed edge and seed center regions. The phenomenon of convex shape and tensile stress difference are completely eliminated by using the PSG/SiO$\_$2/ capping layer. The characterization of SOI films are showed that the SOI films are improved in wetting properties. N channel SOI MOSFET has been fabricated to investigate the electrical characteristics of the recrystallized SOI films. In the 0.7.mu.m thickness SOI MOSFET, kink effects due to the floating substrate occur and the electron mobility was calculated from the measured g$\_$m/ characteristics, which is about 589cm$\^$2//V.s. The recrystallized SOI films are shown to be a good single crystal silicon.

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Hydrogenated Amorphous Silicon Thin Films as Passivation Layers Deposited by Microwave Remote-PECVD for Heterojunction Solar Cells

  • Jeon, Min-Sung;Kamisako, Koichi
    • Transactions on Electrical and Electronic Materials
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    • 제10권3호
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    • pp.75-79
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    • 2009
  • An intrinsic silicon thin film passivation layer is deposited by the microwave remote-plasma enhanced chemical vapor deposition at temperature of $175^{\circ}C$ and various gas ratios for solar cell applications. The good quality amorphous silicon films were formed at silane $(SiH_4)$ gas flow rates above 15 seem. The highest effective carrier lifetime was obtained at the $SiH_4$, flow rate of 20 seem and the value was about 3 times higher compared with the bulk lifetime of 5.6 ${\mu}s$ at a fixed injection level of ${\Delta}n\;=\;5{\times}10^{14}\;cm^{-3}$. An annealing treatment was performed and the carrier life times were increased approximately 5 times compared with the bulk lifetime. The optimal annealing temperature and time were obtained at 250 $^{\circ}C$ and 60 sec respectively. This indicates that the combination of the deposition of an amorphous thin film at a low temperature and the annealing treatment contributes to the excellent surface and bulk passivation.

SOI 응용을 위한 반도체-원자 초격자 구조의 특성 (Characteristics of Semiconductor-Atomic Superlattice for SOI Applications)

  • 서용진;박성우;이경진;김기욱;박창준
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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    • pp.180-183
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    • 2003
  • The monolayer of oxygen atoms sandwitched between the adjacent nanocrystalline silicon layers was formed by ultra high vacuum-chemical vapor deposition (UHV-CVD). This multi-layer Si-O structure forms a new type of superlattice, semiconductor-atomic superattice (SAS). According to the experimental results, high-resolution cross-sectional transmission electron microscopy (HRTEM) shows epitaxial system. Also, the current-voltage (I-V) measurement results show the stable and good insulating behavior with high breakdown voltage. It is apparent that the system may form an epitaxially grown insulating layer as possible replacement of silicon-on-insulator (SOI), a scheme investigated as future generation of high efficient and high density CMOS on SOI.

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N형 양면 수광 태양전지를 위한 레이저 공정의 후면 패시베이션 적층 구조 영향성 (Effect of Laser Ablation on Rear Passivation Stack for N-type Bifacial Solar Cell Application)

  • 김기륜;장효식
    • 한국재료학회지
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    • 제30권5호
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    • pp.262-266
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    • 2020
  • In this paper, we investigated the effect of the passivation stack with Al2O3, hydrogenated silicon nitride (SiNx:H) stack and Al2O3, silicon oxynitride (SiONx) stack in the n type bifacial solar cell on monocrystalline silicon. SiNx:H and SiONx films were deposited by plasma enhanced chemical vapor deposition on the Al2O3 thin film deposited by thermal atomic layer deposition. We focus on passivation properties of the two stack structure after laser ablation process in order to improve bifaciality of the cell. Our results showed SiNx:H with Al2O3 stack is 10 mV higher in implied open circuit voltage and 60 ㎲ higher in minority carrier lifetime than SiONx with Al2O3 stack at Ni silicide formation temperature for 1.8% open area ratio. This can be explained by hydrogen passivation at the Al2O3/Si interface and Al2O3 layer of laser damaged area during annealing.

전하보유모델에 기초한 SONOS 플래시 메모리의 전하 저장층 두께에 따른 트랩 분석 (Analysis of Trap Dependence on Charge Trapping Layer Thickness in SONOS Flash Memory Devices Based on Charge Retention Model)

  • 송유민;정준교;성재영;이가원
    • 반도체디스플레이기술학회지
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    • 제18권4호
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    • pp.134-137
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    • 2019
  • In this paper, the data retention characteristics were analyzed to find out the thickness effect on the trap energy distribution of silicon nitride in the silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices. The nitride films were prepared by low pressure chemical vapor deposition (LPCVD). The flat band voltage shift in the programmed device was measured at the elevated temperatures to observe the thermal excitation of electrons from the nitride traps in the retention mode. The trap energy distribution was extracted using the charge decay rates and the experimental results show that the portion of the shallow interface trap in the total nitride trap amount including interface and bulk trap increases as the nitride thickness decreases.

다층 및 불균일 SiON 박막을 이용한 광간섭필터의 설계 및 제작 (Design and Fabrication Optical Interference Filters using Multiple and Inhomogeneous Dielectric Layers)

  • Lim, Sung kyoo
    • 전자공학회논문지A
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    • 제32A권11호
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    • pp.44-51
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    • 1995
  • Homogeneous, compositionally graded, and superlattice-like silicon oxynitride(SiON) dielectric layers, with the refractive index varying from 1.46 to 2.05 as a function of film thickness, were grown by computer-controlled plasma-enhanced chemical vapor deposition (PECVD) using silane, nitrogen, and nitrous oxide reactant gases. An antireflection(AR) coating and thin-film electroluminescent(TFEL) devices with multiple dielectrics were designed and fabricated using real time control of reactant gases of the PECVD system.

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Field emission characteristics of carbon nanfiber bundles

  • Kim, Sung-Hoon
    • 한국결정성장학회지
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    • 제14권5호
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    • pp.211-214
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    • 2004
  • Carbon nanofiber bundles were formed on silicon substrate using microwave plasma-enhanced chemical vapor deposition system. These bundles were vertically well-grown under the high negative bias voltage condition. The bundles were composed of the individual carbon nanofiber having less than 100 nm diameters. Turn-on voltage of the field emission was measured around 0.8 V/$\mu\textrm{m}$. Fowler-Nordheim plot of the measured values confirmed the field emission characteristic of the measured current.

ECR PECVD 에 의한 상온 실리콘 산화막 형성 (Room Temperature Fabrication of Silicon Oxide Thin Films by ECR PECVD)

  • 이호영;전유찬;주승기
    • 한국진공학회지
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    • 제2권4호
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    • pp.462-467
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    • 1993
  • ECR PECVD(Electron Cyclotron Resonance Plasma Enhanced Chemical Vapor Deposition )장치를 이용하여 (100) 실리콘 기판 위에 실리콘 산화막을 상온에서 증착하였다. 기체 유량비(SiH4/O2)가 막의 성질에 미치는 영향을 고찰하여 최적의 증착 조건을 도출하였다. 기체 유량비가 0.071일 때 비가역 파괴 전장은 9~10MV/cm 이었고, 4~5MV/cmm의 전장하에서 누설 전류는 ~10-11 A/$ extrm{cm}^2$이었다. 이러한 수치들은 액정 표시 소자용 박막 트랜지스터와 같이 저온의 제조공정이 요구되는 소자를 만들기에 충분하다.

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