• Journal of the Korean Ceramic Society
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• v.35 no.6
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• pp.535-542
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• 1998

SOI(silicon oninsulator) was fabricated through the direct bonding of a hydrophilized single crystal Si wafer and a thermally oxidized SiO2 thin film to investigate the stacking faults in silicon at the Si/SiO2 in-terface. At first the oxidation kinetics of SiO2 thin film and the stacking fault distribution at the oxidation interface were investigated. The stacking faults could be divided into two groups by their size and the small-er ones were incorporated into the larger ones as the oxidation time and temperature increased. The den-sity of the smaller ones based critically lower eventually. The SOI wafers directly bonded at the room temperature were annealed at 120$0^{\circ}C$ for 1 hour. The stacking faults at the bonding and oxidation interface were examined and there were anomalies in the distributions of the stacking faults of the bonded region to arrange in ordered ring-like fashion.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 1998.04a
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• pp.91-96
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• 1998

In recent years, the tribological behavior of coated ceramic material has been the topic of much interest. Particularly, the understanding of the tribological performance of thin film under light load is important for potential applications in MEMS. In this work under light load and low speed, the tribological behavior of coated silicon was investigated. The results show that both adhesive and abrasive wear occur depending on the sliding condition. Also the effect of humidity on friction was influenced by the apparent ares of contact between the two surfaces. Finally, undulations on the silicon wafer were found to be effective in trapping wear particles.

• Tribology and Lubricants
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• v.15 no.1
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• pp.29-38
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• 1999

In recent years, the tribological behavior of coated ceramic material has been the issue of much interest. Particularly, the understanding of the tribological performance of thin film under light load is important for its potential in applications of MEMS. The friction and wear behavior of ceramic material that occur at light load depends on several factors such as surface roughness, contact area and material properties. In this work, the tribological behavior of coated silicon under light load and low speed was investigated. Particularly, the effects of coated materials, humidity and undulated surface were also studied. The results show that the effect of humidity on fiction was influenced by the apparent area of contact between the two surfaces. Also both adhesive and abrasive wear occurred depending on the sliding condition. Finally, undulations on the silicon wafer were found to be effective in trapping wear particles and resulted in the reduction of friction.

• 한국신재생에너지학회:학술대회논문집
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• 2009.11a
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• pp.346-346
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• 2009

For high efficiency hetero junction solar cell over 20%, good silicon wafer passivation is one of the most important technological factor. Compared to the conventional PECVD technique, HWCVD has appeared as an promising alternative for high quality passivation layer formation. In this work, HWCVD passivation layer characteristics have been intensively investigated on wafer surface treatment, Hydrogen density in deposited thin layer and thermal effects in deposition process. Comprehensive results of the individual process factors on interface passivation has been discussed and resultant silicon hetero junction solar cell characteristics has been investigated.

• Journal of the Semiconductor & Display Technology
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• v.1 no.1
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• pp.9-13
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• 2002

A polyimide-type electrostatic chuck (ESC) was fabricated for the application of holding 8-inch silicon wafers in the oxide etching equipment. For the fabrication of the unipolar ESC, core technologies such as coating of polyimide films and anodizing treatment of aluminum surface were developed. The polyimide films were prepared on top of thin coated copper substrates for the good electrical contacts, and the helium gas cooling technique was used for the temperature uniformity of the silicon wafers. The ESC was essentially working with an unipolar operation, which was easier to fabricate and operate compared to a bipolar operation. The chucking force of the ESC has been measured to be about 580 gf when the applied voltage was 1.5 kV, which was considered to be enough force to hold wafers during the dry etching processing. The employment of the ESC in etcher system could make 8% enhancement of the wafer processing yield.

• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.131-145
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• 1992

This paper has been described a process technology for the fabrication of Si-on-insulator(SOI) transducers and circuits. The technology utilizes Si-wafer direct bonding(SDB) and mechanical-chemical(M-C) local polishing to create a SOI structure with a high-qualify, uniformly thin layer of single-crystal Si. The electrical and piezoresistive properties of the resultant thin SOI films have been investigated by SOI MOSFET's and cantilever beams, and confirmed comparable to those of bulk Si. Two kinds of pressure transducers using a SOI structure have been proposed. The shifts in sensitivity and offset voltage of the implemented pressure transducers using interfacial $SiO_{2}$ films as the dielectrical isolation layer of piezoresistors were less than -0.2% and +0.15%, respectively, in the temperature range from $-20^{\circ}C$ to $+350^{\circ}C$. In the case of pressure transducers using interfacial $SiO_{2}$ films as an etch-stop layer during the fabrication of thin Si membranes, the pressure sensitivity variation can be controlled to within a standard deviation of ${\pm}2.3%$ from wafer to wafer. From these results, the developed SDB process and the resultant SOI films will offer significant advantages in the fabrication of integrated microtransducers and circuits.

• The Korean Journal of Ceramics
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• v.7 no.1
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• pp.36-40
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• 2001

In order to fabricate uncooled IR sensors for pyroelectric applications, multilayered thin films of Pt/PbTiO$_3$/Pt/Ti/Si$_3$N$_4$/SiO$_2$/Si and thermally isolating membrane structures of square-shaped/cantilevers-shaped microstructures were prepared. Cavity was also fabricated via direct silicon wafer bonding and etching technique. Metallic Pt layer was deposited by ion beam sputtering while PbTiO$_3$ thin films were prepared by sol-gel technique. Micromachining technology was used to fabricate microstructured-membrane detectors. In order to avoid a difficulty of etching active layers, silicon-nitride membrane structure was fabricated through the direct bonding and etching of the silicon wafer. Although multilayered thin film deposition and device fabrications were processed independently, these could b integrated to make IR micro-sensor devices.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.865-871
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• 2014

Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.46.1-46.1
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• 2010

Surface passivation of crystalline silicon(c-Si) surface with a-Si:H thin films has been investigated by using quasi-steady-state photo conductance(QSSPC) measurements. Analyzing the influence of a-Si:H film thickness, process gas ratio, deposition temperature and post annealing temperature on the passivation properties of c-Si, we optimized the passivation conditions at the substrate temperature of $200-250^{\circ}C$. Best surface passivation has been obtained by post-deposition annealing of a-Si:H film layer. Post annealing around the deposition temperature was sufficient to improve the surface passivation for silicon substrates. We obtained effective carrier lifetimes above 5.5 ms on average.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.8
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• pp.708-713
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• 2005

An alumina membrane with nano-sized pore array by anodic oxidation using the thin film aluminum deposited on silicon wafer was fabricated. It Is important that the sample prepared by metal deposition method has a flat aluminum surface and a good adhesion between the silicon wafer and the thin film aluminum. The oxidation time was controlled by observation of current variation. While the oxalic acid with 0.2 M was used for low voltage anodization under 100 V, the chromic acid with 0.1 M was used for high voltage anodization over 100 V. The nano-sized pores with diameter of $60\~120$ nm was obtained by low voltage anodization of $40\~80$ V and those of $200\~300$ nm was obtained by high voltage anodization of $140\~200$ V. The pore widening process was employed for obtaining the one-channel with flat surface because the pores of the alumina membrane prepared by the fixed voltage method shows the structure of two-channel with rough surface. Finally, the sample was immersed to the phosphoric acid with 0.1 M concentration to etching the barrier layer.