• Proceedings of the Materials Research Society of Korea Conference
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• 1992.05b
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• pp.57-58
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• 1992

The NH$_3$oxidation, which forms thermal oxide layer on silicon substrate with pure $O_2$gas added with small amounts of NH$_3$gas, has good interface sates due to activated gettering effect during oxidation. The superiority of interfae state in NH$_3$ oxidation method is not affected by preprocess but by gettering during oxidation. The dramatec reduction fo interface state is conformed with observing OSF when NH$_3$ oxide is annealed in NH$_3$ atmosphere.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.83-90
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• 1998

The effects of dopant activation anneal on GOI (Gate Oxide Integrity) of MOS capacitor with amorphous silicon gate electrode were investigated. It was found that the amorphous silicon gate electrode was crystallized and the dopant atoms were sufficiently activated by activation anneal. The mechanical stress of gate electrode that reveals large compressive stress in amorphous state, was released with increase of anneal temperature from $700^{\circ}C$ to 90$0^{\circ}C$. The resistivity of gate electrode polycrystalline silicon film is decreased by the increase of anneal temperature. The reliability of thin gate oxide and interface properties between oxide and silicon substrate greatly depends on the activation anneal temperature. The charge trapping characteristics as well as oxide reliability are improved by the anneal of 90$0^{\circ}C$ compare to that of $700^{\circ}C$ or 80$0^{\circ}C$. Especially, the lifetimes of the thin gate oxide estimated by TDDB method is 3$\times$10$^{10}$ for the case of $700^{\circ}C$ anneal, is significantly increased to 2$\times$10$^{12}$ for the case of 90$0^{\circ}C$ anneal. Finally, the interface trap density is reduced with relaxation of mechanical stress of gate electrode.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2518-2520
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• 1998

Silicon can be reactive ion etched (RIE) either isotropically or anisotropically. In this paper, a new micromachining technology combining these two etching characteristics is proposed. In the proposed method, the fabrication steps are as follows. First. a polysilicon layer, which is used as the bottom electrode, is deposited on the silicon wafer and patterned. Then the silicon substrate is etched anisotropically to a few micrometer depth that forms a cavity. Then an PECVD oxide layer is deposited to passivate the cavity side walls. The oxide layers at the top and bottom faces are removed while the passivation layers of the side walls are left. Then the substrate is etched again but in an isotropic etch condition to form a round trench with a larger radius than the anisotropic cavity. Then a sacrificial PECVD oxide layer is deposited and patterned. Then a polysilicon structural layer is deposited and patterned. This polysilicon layer forms a pivot structure of a rocker-arm. Finally, oxide sacrificial layers are etched away. This new micromachining technology is quite simpler than conventional method to fabricate joint structures, and the devices that are fabricated using this technology do not require a flexing structure for motion.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.252-254
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• 2002

Metal oxides with high dielectric constants have the potential to expend scaling of transistor gate capacitance beyond that of ultrathin silicon dioxide. However, during deposition of most metal oxides on silicon, an interfacial region of SiOx is formed and limits the specific capacitance of the gate structure. We deposisted aluminum oxide and examined the composition of the interfacial layer by employing high-resolution X-ray photoelectron spectroscopy and X-ray reflectivity. We find that the interfacial region is not pure SiO$_2$, but is composed of a complex depth-dependent ternary oxide of $AlSi_xO_y$ and the pure SiO$_2$.

• Journal of Korean Vacuum Science & Technology
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• v.3 no.1
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• pp.54-58
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• 1999

We deposited diamond-like carbon (DLC) films using ion beam sputtering of a graphite target on flat substrates for use as a thin film field emitter. An n-type silicon wafer, titanium-coated silicon, and indium tin oxide (ITO) coated glass were used as a substrate. All films exhibited a sudden increase in the emission after a breakdown occurred at high voltage. The morphology of the films after the breakdown depended on the substrate. On ITO and Ti substrates, the DLC film peeled off upon breakdown, but on the Si substrate the surface melting due to breakdown resulted in the formation of various structures such as a sharp point, mound, and crater. By scanning the deformed surface with a tip anode, we found that the emission was concentrated at the deformed sites, indicating that the field enhancement due to the morphology change was responsible for the increased emission.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.1
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• pp.25-32
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• 2007

We investigated the silicide reaction stability between 10 nm-Col-xNix alloy films and silicon substrates with the existence of 4 nm-thick natural oxide layers. We thermally evaporated 10 nm-Col-xNix alloy films by varying $x=0.1{\sim}0.9$ on naturally oxidized single crystal and 70 nm-thick polycrystalline silicon substrates. The films structures were annealed by rapid thermal annealing (RTA) from $600^{\circ}C$ to $1100^{\circ}C$ for 40 seconds with the purpose of silicidation. After the removal of residual metallic residue with sulfuric acid, the sheet resistance, microstructure, composition, and surface roughness were investigated using a four-point probe, a field emission scanning electron microscope, a field ion bean4 an X-ray diffractometer, and an Auger electron depth profiling spectroscope, respectively, to confirm the silicide reaction. The residual stress of silicon substrate was also analyzed using a micro-Raman spectrometer We report that the silicide reaction does not occur if natural oxides are present. Metallic oxide residues may be present on a polysilicon substrate at high silicidation temperatures. Huge residual stress is possible on a single crystal silicon substrate at high temperature, and these may result in micro-pinholes. Our results imply that the natural oxide layer removal process is of importance to ensure the successful completion of the silicide process with CoNi alloy films.

• Journal of the Optical Society of Korea
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• v.18 no.6
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• pp.685-690
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• 2014

Microholographic gratings were prepared on an aluminum oxide ($Al_2O_3$) surface using a 140-fs pulse at a center wavelength of 800 nm. The $Al_2O_3$ was deposited on a silicon wafer and on indium tin oxide glass to a thickness of approximately 25 nm using an atomic layer deposition process. The silicon wafer substrate exhibited reflection-type gratings that were measured as a function of the incidence angle. The diffraction efficiency of the fabricated gratings was measured, with a maximum diffraction efficiency of 45% at an incidence angle of approximately $30^{\circ}$.

• ETRI Journal
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• v.28 no.3
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• pp.389-392
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• 2006

In this letter, a laterally-driven bistable electromagnetic microrelay is designed, fabricated, and tested. The proposed microrelay consists of a pair of arch-shaped leaf springs, a shuttle, and a contact bar made from silicon, low temperature oxide (LTO), and gold composite materials. Silicon-on-insulator wafers are used for electrical isolation and releasing of the moving microstructures. The high-aspect-ratio microstructures are fabricated using a deep reactive ion etching (DRIE) process. The tandem-typed leaf springs with a silicon/gold composite layer enhance the mechanical performances while reducing the electrical resistance. A permanent magnet is attached at the bottom of the silicon substrate, resulting in the generation of an external magnetic field in the direction vertical to the surface of the silicon substrate. The leaf springs show bistable characteristics. The resistance of the pair of leaf springs was $7.5\;{\Omega}$, and the contact resistance was $7.7\;{\Omega}$. The relay was operated at ${\pm}0.12\;V$.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1440-1441
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• 1995

We fabricated diode-type silicon field emitter array device and tested the current-voltage characteristics. Silicon oxide layer having the thickness of $1{\mu}m$ is grown in the (100) oriented n-type silicon substrates. Oxide layer is patterned by the mask with $10{\mu}m$ diameter circles. Silicon substrate is then etched using NAF 1 solution to form the sharp tip arrays as an electron source. In the UHV test station, we tested the current-voltage characteristics for the samples. Turn-on voltage was about 140V and maximum emission current was $310{\mu}A$ at 164V. We studied about silicon bonding process for future work, too.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.9
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• pp.378-382
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• 2003

Transparent conductive oxides (TCO) are necessary as front electrode for most thin film solar cell. In our paper, transparent conducting aluminum-doped Zinc oxide films (ZnO:Al) were prepared by rf magnetron sputtering on glass (Corning 1737) substrate as a variation of the deposition condition. After deposition, the smooth ZnO:Al films were etched in diluted HCI (0.5%) to examine the electrical and surface morphology properties as a variation of the time. The most important deposition condition of surface-textured ZnO films by chemical etching is the processing pressure md the substrate temperature. In low pressures (0.9mTorr) and high substrate temperatures ($\leq$$300^{\circ}C$), the surface morphology of films exhibits a more dense and compact film structure with effective light-trapping to apply the silicon thin film solar cells.