• Korean Chemical Engineering Research
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• 제48권2호
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• pp.218-223
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• 2010

본 연구에서는 반도체식 가스센서 재료로서 활용 가능한 ZnO 박막을 Continuous Flow Reaction(CFR) 방법으로 실리콘 기판 위에 성장시켰다. 또한 전구물질로 사용한 zinc acetate의 농도에 따른 산화아연 박막의 성장특성과 이들의 전기적 특성이 조사되었다. 산화아연 박막 제조는 0.005~0.02 M의 zinc acetate 농도에서 수행되었다. 산화아연 박막을 구성하고 있는 ZnO의 입자크기는 농도가 증가할수록 증가되었으며, 박막의 두께도 함께 증가되었다. CFR 법에 의한 산화아연 박막의 성장속도는 전구물질의 농도에 비례적으로 의존되는 것을 확인하였으며, 균일한 박막을 제조하기 위한 전구물질의 최적 농도는 0.01 M이였다. 한편, 전구물질의 농도를 달리하여 제조된 산화아연 박막의 전압에 대한 전류를 I-V 측정기로 측정한 결과, 박막의 두께가 증가될수록 높은 전류가 흘렀다. 그러므로 산화아연 박막의 전류를 전구물질의 농도변화로 조절할 수 있다. 또한 산화아연 박막을 $300^{\circ}C$에서 5 min 동안 $500ppmv\;H_2S$에 노출시킨 결과, 전압에 대한 전류값이 낮아졌다. 이와 같이 산화아연의 전기적 특성은 가스센서로 응용할 수 있는 가능성을 확인시켜 주는 결과라 할 수 있다.

• 센서학회지
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• 제11권3호
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• pp.183-190
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• 2002

실리콘 기판 위에 형성한 열산화막에 실리콘이온을 주입하고 열처리를 수행한 후, 광루미네센스(photoluminescence:PL) 스펙트럼을 조사하였다. 실리콘 이온도즈의 변화와 열처리 온도의 변화에 따른 PL스펙트럼을 조사하고, 이를 TEM과 XRD 데이터와 비교하여 분석한 결과, 광루미네센스 특성은 산화막내의 실리콘 나노결정으로부터 기인함을 알 수 있었다. 또 산화막을 1분 간격으로 습식 식각하면서 매 식각 시마다 PL스펙트럼을 관측하여 그 변화를 조사하였다. 이러한 실험을 통하여 산화막내에 분포하고 있는 실리콘 나노결정의 크기와 그 수가 PL피크 파장과 강도에 직접적으로 영향을 줌을 알 수 있었다.

• Tribology and Lubricants
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• 제39권2호
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• pp.72-75
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• 2023

Silicon carbide (SiC) is used as a substrate material for power semiconductors; however, SiC chemical mechanical polishing (CMP) requires considerable time owing to its chemical stability and high hardness. Therefore, researchers are attempting to increase the material removal rate (MRR) of SiC CMP using various methods. Mixed-abrasive CMP (MAS CMP) is one method of increasing the material removal efficiency of CMP by mixing two or more particles. The aim of this research is to study the mathematical modeling of the MRR of MAS CMP of SiC with SiO₂ and TiO₂ particles. With a total particle concentration of 32 wt, using 80-nm SiO₂ particles and 25-nm TiO₂ particles maximizes the MRR at 8 wt of the TiO₂ particle concentration. In the case of 5 nm TiO₂ particles, the MRR tends to increase with an increase in TiO₂ concentration. In the case of particle size 10-25 nm TiO₂, as the particle concentration increases, the MRR increases to a certain level and then decreases again. TiO₂ particles of 25 nm or more continuously decreased MRR as the particle concentration increased. In the model proposed in this study, the MRR of MAS CMP of SiC increases linearly with changes in pressure and relative speed, which shows the same result as the Preston's equation. These results can contribute to the future design of MAS; however, the model needs to be verified and improved in future experiments.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.422.1-422.1
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• 2016

Graphene quantum dots (GQDs), a new kind of carbon-based photo luminescent nanomaterial from chemically modified graphene oxide (CMGO) or chemically modified graphene (CMG), has attracted extensive research attention in the last few years due to its outstanding chemical, optical and electrical properties. To further extended its potential applications as optoelectronic devices, solar cells, bio and bio-sensors and so on, intensive research efforts have been devoted to the CMG. However, the CMG, a suspension of aqueous, have problematic since they are prone to agglomeration after drying a solvent. In this study, we synthesized the GQDs from graphite and deposited on silicon substrate by kinetic spray. The photo luminescent properties of deposited GQD films were analyzed and compared with initial GQDs suspension. In addition, its carbon properties were investigated with GQDs solution properties. The properties of deposited GQD films by kinetic spray were similar to that of the GQDs suspension in water. We could provide a pathway for silicon-based silicon based device applications. Finally, the well-adjusted GQD films with photo luminescence effects will show Energy-Down-Shift layer effects on silicon solar cells. The GQD layers deposited at nozzle scan speeds of 40, 30, 20, and 10 mm/s were evaluated after they were used to fabricate crystalline-silicon solar cells; the results indicate that GQDs play an important role in increasing the optical absorptivity of the cells. The short-circuit current density (Jsc) was enhanced by about 2.94 % (0.9 mA/cm2) at 30 mm/s. Compared to a reference device without a GQD energy-down-shift layer, the PCE of p-type silicon solar cells was improved by 2.7% (0.4 percentage points).

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.277-277
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• 2013

The epitaxial graphene on the 4H- or 6H-SiC(0001) surface has been intensively studied due to the possibility of wafer-scale growt. However the existence of interface layer (zero layer graphene) and its influence on the upper graphene layer have been considered as one of the main obstarcles for the industrial application. Among various methods tried to overcome the strong interaction with the substrate through the interface layer, it has been proved that the hydrogen intercalation successfully passivate the Si dangling bond of the substrate and can produce the quasi-free standing epitaxial graphene (QFEG) layers on the siC(0001) surface. In this study, we report the results of the angle-resolved photoemission spectroscopy (ARPES) and Raman spectroscopy for the QFEG layers produced by ex-situ and in-situ hydrogen intercalation.From the ARPES measurement, we confirmed that the Dirac points of QFEG layers exactly coincide with the Fermi level. The band structure of QFEG layer are sustainable upon thermal heating up to 1100 K and robust against the deposition of several metals andmolecular deposition. We also investigated the strain of the QFEG layers by using Raman spectroscopy measurement. From the change of the 2D peak position of graphene Raman spectrum, we found out that unlike the strong compressive strain in the normal epitaxial graphene on the SiC(0001) surface, the strain of the QFEG layer are significantly released and almost similar to that of the mechanically exfoliated graphene on the silicon oxide substrate. These results indicated that various ideas proposed for the ideal free-standing graphene can be tested based on the QFEG graphene layers grown on the SiC(0001) surface.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 춘계학술대회 초록집
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• pp.59.1-59.1
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• 2010

Aluminum-induced crystallization (AIC) of amorphous silicon (a-Si) is studied with the structure of a glass/Al/$SiO_2$/a-Si, in which the $SiO_2$ layer has micron-sized laser holes in the stack. An oxide layer between aluminum and a-Si thin films plays a significant role in the metal-induced crystallization (MIC) process determining the properties such as grain size and preferential orientation. In our case, the crystallization of a-Si is carried out only through the key hole because the $SiO_2$ layer is substantially thick enough to prevent a-Si from contacting aluminum. The crystal growth is successfully realized toward the only vertical direction, resulting a crystalline silicon grain with a size of $3{\sim}4{\mu}m$ under the hole. Lateral growth seems to be not occurred. For the AIC experiment, the glass/Al/$SiO_2$/a-Si stacks were prepared where an Al layer was deposited on glass substrate by DC sputter, $SiO_2$ and a-Si films by PECVD method, respectively. Prior to the a-Si deposition, a $30{\times}30$ micron-sized hole array with a diameter of $1{\sim}2{\mu}m$ was fabricated utilizing the femtosecond laser pulses to induce the AIC process through the key holes and the prepared workpieces were annealed in a thermal chamber for 2 hours. After heat treatment, the surface morphology, grain size, and crystal orientation of the polycrystalline silicon (pc-Si) film were evaluated by scanning electron microscope, transmission electron microscope, and energy dispersive spectrometer. In conclusion, we observed that the vertical crystal growth was occurred in the case of the crystallization of a-Si with aluminum by the MIC process in a small area. The pc-Si grain grew under the key hole up to a size of $3{\sim}4{\mu}m$ with the workpiece.

• 한국재료학회지
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• 제19권1호
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• pp.37-43
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• 2009

Silicon dioxide as gate dielectrics was grown at $400^{\circ}C$ on a polycrystalline Si substrate by inductively coupled plasma oxidation using a mixture of $O_2$ and $N_2O$ to improve the performance of polycrystalline Si thin film transistors. In conventional high-temperature $N_2O$ annealing, nitrogen can be supplied to the $Si/SiO_2$ interface because a NO molecule can diffuse through the oxide. However, it was found that nitrogen cannot be supplied to the Si/$SiO_2$ interface by plasma oxidation as the $N_2O$ molecule is broken in the plasma and because a dense Si-N bond is formed at the $SiO_2$ surface, preventing further diffusion of nitrogen into the oxide. Nitrogen was added to the $Si/SiO_2$ interface by the plasma oxidation of mixtures of $O_2/N_2O$ gas, leading to an enhancement of the field effect mobility of polycrystalline Si TFTs due to the reduction in the number of trap densities at the interface and at the Si grain boundaries due to nitrogen passivation.

• 한국결정성장학회지
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• 제11권5호
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• pp.224-230
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• 2001

초박막 게이트 유전막 및 비휘발성 기억소자의 게이트 유전막으로 연구되고 있는 $NO/N_2O$ 열처리된 재산화 질화산 화막의 특성을 D-SIMS(Dynamic Secondary Ion Mass Spectrometry), ToF-SIMS(Time-of-Flight Secondary Ion Mass Spectrometry), AES(Auger Electron Spectroscopy)으로 조사하였다. 시료는 초기산화막 공정후에 NO 및 $N_2O$ 열처리를 수행하였으며, 다시 재산화공정을 통하여 질화산화막내 질소의 재분포를 형성토록하였다. 재산화에 있어서 습식산화시 공정에 사용된 수소에 의한 영향으로 계면 근처에 축적된 질소가 Si≡N 결합을 쉽게 이탈함에 따라 방출이 촉진되어 건식산화에 비하여 질소의 감소가 더욱 두드러지게 나타났다. 재산화에 따른 질화산화막내 질소의 거동은 외부로의 방출과 기판으로의 확산이 동시에 나타난다. 재산화후 질화산화막내 축적된 질소의 결합종을 분석한 결과, 초기산화막 계면근처의 질소는 SiON의 결합종이 주도적으로 나타나는 반면 재산화 후 새롭게 형성된 $Si-SiO_2$ 계면근처로 확산한 질소는 $Si_2NO$ 결합종이 주로 검출된다. SiON에 의한 질소의 미결합손과 $Si_2$NO에 의한 실리콘의 미겨랍손은 기억특성에 기여하는 결함을 포함하기 때문에 재산화 질화산화막내 존재하는 SiON과 $Si_2$NO 결합종은 모두 전하트랩의 기원과 관련된 결합상태로 예상된다.

• 한국표면공학회지
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• 제29권6호
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• pp.809-815
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• 1996

$Y_2O_3$-based metal-insulator-semiconductor (MIS) structure on p-Si(100) has been studied. Films were prepared by UHV reactive ionized cluster beam deposition (r-ICBD) system. The base pressure of the system was about $1 \times 10^{-9}$ -9/ Torr and the process pressure $2 \times 10^{-5}$ Torr in oxygen ambience. Glancing X-ray diffraction(GXRD) and in-situ reflection high energy electron diffracton(RHEED) analyses were performed to investigate the crystallinity of the films. The results show phase change from amorphous state to crystalline one with increasingqr acceleration voltage and substrate temperature. It is also found that the phase transformation from $Y_2O_3$(111)//Si(100) to $Y_2O_3$(110)//Si(100) in growing directions takes place between $500^{\circ}C$ and $700^{\circ}C$. Especially as acceleration voltage is increased, preferentially oriented crystallinity was increased. Finally under the condition of above substrate temperature $700^{\circ}C$ and acceleration voltage 5kV, the $Y_2O_3$films are found to be grown epitaxially in direction of $Y_2O_3$(1l0)//Si(100) by observation of transmission electron microscope(TEM). Capacitance-voltage and current-voltage measurements were conducted to characterize Al/$Y_2O_3$/Si MIS structure with varying acceleration voltage and substrate temperature. Deposited $Y_2O_3$ films of thickness of nearly 300$\AA$ show that the breakdown field increases to 7~8MV /cm at the same conditon of epitaxial growing. These results also coincide with XPS spectra which indicate better stoichiometric characteristic in the condition of better crystalline one. After oxidation the breakdown field increases to 13MV /cm because the MIS structure contains interface silicon oxide of about 30$\AA$. In this case the dielectric constant of only $Y_2O_3$ layer is found to be $\in$15.6. These results have demonstrated the potential of using yttrium oxide for future VLSI/ULSI gate insulator applications.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.151-151
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• 2009

Recently, there has been increasing interest in amorphous oxide semiconductors to find alternative materials for an amorphous silicon or organic semiconductor layer as a channel in thin film transistors(TFTs) for transparent electronic devices owing to their high mobility and low photo-sensitivity. The fabriction of amorphous oxide-based TFTs at room temperature on plastic substrates is a key technology to realize transparent flexible electronics. Amorphous oxides allows for controllable conductivity, which permits it to be used both as a transparent semiconductor or conductor, and so to be used both as active and source/drain layers in TFTs. One of the materials that is being responsible for this revolution in the electronics is indium-zinc-tin oxide(IZTO). Since this is relatively new material, it is important to study the properties of room-temperature deposited IZTO thin films and exploration in a possible integration of the material in flexible TFT devices. In this research, we deposited IZTO thin films on polyethylene naphthalate substrate at room temperature by using magnetron sputtering system and investigated their properties. Furthermore, we revealed the fabrication and characteristics of top-gate-type transparent TFTs with IZTO layers, seen in Fig. 1. The experimental results show that by varying the oxygen flow rate during deposition, it can be prepared the IZTO thin films of two-types; One a conductive film that exhibits a resistivity of $2\times10^{-4}$ ohm${\cdot}$cm; the other, semiconductor film with a resistivity of 9 ohm${\cdot}$cm. The TFT devices with IZTO layers are optically transparent in visible region and operate in enhancement mode. The threshold voltage, field effect mobility, on-off current ratio, and sub-threshold slope of the TFT are -0.5 V, $7.2\;cm^2/Vs$, $\sim10^7$ and 0.2 V/decade, respectively. These results will contribute to applications of select TFT to transparent flexible electronics.