• 제목/요약/키워드: Silicon oxide substrate

검색결과 238건 처리시간 0.022초

게이트 산화막에 대한 암모니아 어닐링의 효과 (The Effect of $NH_3$ Annealing for Gate Oxide)

  • 김영조;김철주
    • 한국재료학회:학술대회논문집
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    • 한국재료학회 1992년도 춘계학술발표회
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    • pp.57-58
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    • 1992
  • The NH$_3$oxidation, which forms thermal oxide layer on silicon substrate with pure $O_2$gas added with small amounts of NH$_3$gas, has good interface sates due to activated gettering effect during oxidation. The superiority of interfae state in NH$_3$ oxidation method is not affected by preprocess but by gettering during oxidation. The dramatec reduction fo interface state is conformed with observing OSF when NH$_3$ oxide is annealed in NH$_3$ atmosphere.

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불순물 활성화 열처리가 MOS 캐패시터의 게이트 전극과 산화막의 특성에 미치는 효과 (Impacts of Dopant Activation Anneal on Characteristics of Gate Electrode and Thin Gate Oxide of MOS Capacitor)

  • 조원주;김응수
    • 전자공학회논문지D
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    • 제35D권10호
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    • pp.83-90
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    • 1998
  • MOS 캐패시터의 게이트 전극을 비정질 상태의 실리콘으로 형성하여 GOI(Gate Oxide Integrity)특성에 미치는 불순물 활성화 열처리의 효과를 조사하였다. LPCVD(Low Pressure Chemical Vapor Deposition) 방법으로 증착한 비정질 실리콘 게이트 전극은 활성화 열처리에 의하여 다결정 실리콘 상태로 구조가 변화하며, 불순물 원자의 활성화가 충분히 이루어졌다. 또한, 비정질 상태의 게이트 전극은 커다란 압축 응력(compressive stress)을 가지지만, 활성화 열처리 온도가 700℃에서 900℃로 증가함에 따라서 응력이 완화되었고 게이트 전극의 저항도 감소하는 특성을 보였다. 또한 얇은 게이트 산화막의 신뢰성 및 산화막의 계면특성은 활성화 열처리 온도에 크게 의존하고 있었다. 900℃에서 활성화 열처리를 한 경우가 700℃에서 열처리한 경우보다 산화막내에서의 전하 포획 특성이 개선되었으며, 산화막의 신뢰성이 향상되었다. 특히, TDDB 방법으로 예측한 게이트 산화막의 수명은 700℃의 열처리에서는 3×10/sup 10/초였지만, 900℃에서의 열처리에서는 2×10/sup 12/초로 현저하게 개선되었다. 그리고, 산화막 계면에서의 계면 전하 밀도는 게이트의 응력 완화에 따라서 개선되었다.

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저전압 구동용 전기스위치와 미러 어레이 응용을 위한 새로운 표면미세가공기술 (A New Surface Micromachining Technology for Low Voltage Actuated Switch and Mirror Arrays)

  • 박상준;이상우;김종팔;이상우;이상철;김성운;조동일
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1998년도 하계학술대회 논문집 G
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    • pp.2518-2520
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    • 1998
  • Silicon can be reactive ion etched (RIE) either isotropically or anisotropically. In this paper, a new micromachining technology combining these two etching characteristics is proposed. In the proposed method, the fabrication steps are as follows. First. a polysilicon layer, which is used as the bottom electrode, is deposited on the silicon wafer and patterned. Then the silicon substrate is etched anisotropically to a few micrometer depth that forms a cavity. Then an PECVD oxide layer is deposited to passivate the cavity side walls. The oxide layers at the top and bottom faces are removed while the passivation layers of the side walls are left. Then the substrate is etched again but in an isotropic etch condition to form a round trench with a larger radius than the anisotropic cavity. Then a sacrificial PECVD oxide layer is deposited and patterned. Then a polysilicon structural layer is deposited and patterned. This polysilicon layer forms a pivot structure of a rocker-arm. Finally, oxide sacrificial layers are etched away. This new micromachining technology is quite simpler than conventional method to fabricate joint structures, and the devices that are fabricated using this technology do not require a flexing structure for motion.

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알루미나와 실리카/실리콘 기판의 계면 분석 (Analysis of Interfacial Layer between Alumina and Silica/Silicon Substrate)

  • 최일상;김영철;장영철
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2002년도 춘계 기술심포지움 논문집
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    • pp.252-254
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    • 2002
  • Metal oxides with high dielectric constants have the potential to expend scaling of transistor gate capacitance beyond that of ultrathin silicon dioxide. However, during deposition of most metal oxides on silicon, an interfacial region of SiOx is formed and limits the specific capacitance of the gate structure. We deposisted aluminum oxide and examined the composition of the interfacial layer by employing high-resolution X-ray photoelectron spectroscopy and X-ray reflectivity. We find that the interfacial region is not pure SiO$_2$, but is composed of a complex depth-dependent ternary oxide of $AlSi_xO_y$ and the pure SiO$_2$.

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Field emission from diamond-like carbon films studied by scanning anode

  • Ahn, S.H.;Jeon, D.;Lee, K.-R.
    • Journal of Korean Vacuum Science & Technology
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    • 제3권1호
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    • pp.54-58
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    • 1999
  • We deposited diamond-like carbon (DLC) films using ion beam sputtering of a graphite target on flat substrates for use as a thin film field emitter. An n-type silicon wafer, titanium-coated silicon, and indium tin oxide (ITO) coated glass were used as a substrate. All films exhibited a sudden increase in the emission after a breakdown occurred at high voltage. The morphology of the films after the breakdown depended on the substrate. On ITO and Ti substrates, the DLC film peeled off upon breakdown, but on the Si substrate the surface melting due to breakdown resulted in the formation of various structures such as a sharp point, mound, and crater. By scanning the deformed surface with a tip anode, we found that the emission was concentrated at the deformed sites, indicating that the field enhancement due to the morphology change was responsible for the increased emission.

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자연산화막 존재에 따른 코발트 니켈 복합실리사이드 공정의 안정성 (Silicidation Reaction Stability with Natural Oxides in Cobalt Nickel Composite Silicide Process)

  • 송오성;김상엽;김종률
    • 한국산학기술학회논문지
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    • 제8권1호
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    • pp.25-32
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    • 2007
  • 코발트 니켈 합금형 실리사이드 공정에서 단결정실리콘과 다결정실리콘 기판에 자연산화막이 있는 경우 나노급 두께의 코발트 니켈 합금 금속을 증착하고 실리사이드화하는 경우의 반응 안정성을 확인하였다. 4인치 P-type(100)Si 기판 전면에 poly silicon을 입힌 기판과 single silicon 상태의 두 종류 기판을 준비하고 두께 4 nm의 자연산화막이 있는 상태에서 10 nm 코발트 니켈 합금을 니켈의 상대조성을 $10{\sim}90%$로 달리하며 열증착하였다. 통상의 600, 700, 800, 900, 1000, $1100^{\circ}C$ 각 온도에서 실리사이드화 열처리를 시행 후 잔류 합금층을 제거하고, XRD(X-ray diffraction)및 FE-SEM(Field emission scanning electron microscopy), AES(Auger electron spectroscopy)를 사용하여 실리사이드가 생겼는지 확인하였다. 마이크로라만 분석기로 실리사이드 반응시의 실리콘 층의 잔류 스트레스도 확인하였다. 자연산화막이 존재하는 경우 실리사이드 반응이 진행되지 않았고, 폴리실리콘 기판과 고온에서는 금속과 산화층의 반응잔류물이 생성되었다. 단결정 기판의 고온열처리에서는 실리사이드 반응이 없더라도 핀홀이 발생할 수 있는 정도의 열스트레스가 존재하였다. 코발트 니켈 복합실리사이드 공정에서는 자연산화막을 제거하는 공정이 필수적이었다.

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Fabrication of Microholographic Gratings on Al2O3 Grown by Atomic Layer Deposition Using a Femtosecond Laser

  • Bang, Le Thanh;Fauzi, Anas;Heo, Kwan-Jun;Kim, Sung-Jin;Kim, Nam
    • Journal of the Optical Society of Korea
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    • 제18권6호
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    • pp.685-690
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    • 2014
  • Microholographic gratings were prepared on an aluminum oxide ($Al_2O_3$) surface using a 140-fs pulse at a center wavelength of 800 nm. The $Al_2O_3$ was deposited on a silicon wafer and on indium tin oxide glass to a thickness of approximately 25 nm using an atomic layer deposition process. The silicon wafer substrate exhibited reflection-type gratings that were measured as a function of the incidence angle. The diffraction efficiency of the fabricated gratings was measured, with a maximum diffraction efficiency of 45% at an incidence angle of approximately $30^{\circ}$.

A Laterally-Driven Bistable Electromagnetic Microrelay

  • Ko, Jong-Soo;Lee, Min-Gon;Han, Jeong-Sam;Go, Jeung-Sang;Shin, Bo-Sung;Lee, Dae-Sik
    • ETRI Journal
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    • 제28권3호
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    • pp.389-392
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    • 2006
  • In this letter, a laterally-driven bistable electromagnetic microrelay is designed, fabricated, and tested. The proposed microrelay consists of a pair of arch-shaped leaf springs, a shuttle, and a contact bar made from silicon, low temperature oxide (LTO), and gold composite materials. Silicon-on-insulator wafers are used for electrical isolation and releasing of the moving microstructures. The high-aspect-ratio microstructures are fabricated using a deep reactive ion etching (DRIE) process. The tandem-typed leaf springs with a silicon/gold composite layer enhance the mechanical performances while reducing the electrical resistance. A permanent magnet is attached at the bottom of the silicon substrate, resulting in the generation of an external magnetic field in the direction vertical to the surface of the silicon substrate. The leaf springs show bistable characteristics. The resistance of the pair of leaf springs was $7.5\;{\Omega}$, and the contact resistance was $7.7\;{\Omega}$. The relay was operated at ${\pm}0.12\;V$.

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다이오드형 실리콘 전계방출소자의 제작 및 특성평가 (Fabrication and Characterization of Diode-Type Si Field Emitter Array)

  • 박흥우;주병권;김성진;정재훈;박정호;오명환
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1995년도 하계학술대회 논문집 C
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    • pp.1440-1441
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    • 1995
  • We fabricated diode-type silicon field emitter array device and tested the current-voltage characteristics. Silicon oxide layer having the thickness of $1{\mu}m$ is grown in the (100) oriented n-type silicon substrates. Oxide layer is patterned by the mask with $10{\mu}m$ diameter circles. Silicon substrate is then etched using NAF 1 solution to form the sharp tip arrays as an electron source. In the UHV test station, we tested the current-voltage characteristics for the samples. Turn-on voltage was about 140V and maximum emission current was $310{\mu}A$ at 164V. We studied about silicon bonding process for future work, too.

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표면 텍스쳐된 ZnO:Al 투명전도막 증착 및 특성 (The Deposition and Properties of Surface Textured ZnO:Al Films)

  • 유진수;이정철;김석기;윤경훈;박이준;이준신
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제52권9호
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    • pp.378-382
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    • 2003
  • Transparent conductive oxides (TCO) are necessary as front electrode for most thin film solar cell. In our paper, transparent conducting aluminum-doped Zinc oxide films (ZnO:Al) were prepared by rf magnetron sputtering on glass (Corning 1737) substrate as a variation of the deposition condition. After deposition, the smooth ZnO:Al films were etched in diluted HCI (0.5%) to examine the electrical and surface morphology properties as a variation of the time. The most important deposition condition of surface-textured ZnO films by chemical etching is the processing pressure md the substrate temperature. In low pressures (0.9mTorr) and high substrate temperatures ($\leq$$300^{\circ}C$), the surface morphology of films exhibits a more dense and compact film structure with effective light-trapping to apply the silicon thin film solar cells.