• 센서학회지
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• 제3권2호
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• pp.74-80
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• 1994

Silicon direct bonding 기술은 잔류 응력이 없고, 안정한 특성을 가진 센서의 제작과 silicon-on-insulator 소자의 제조에 널리 이용되고 있다. SDB의 공정 절차는 크게 실리콘 웨이퍼의 수산화 공정 과정과 wet oxidation fumace에서 고온의 열처리 공정 과정을 거치게 된다. 수산화 공정을 행한 후, Fourier transformation-infrared spectroscopy를 사용하여 실리콘 웨이퍼 표면을 분석하여 보면, 실리콘 웨이퍼의 표면에서는 수산화기가 생성됨을 알 수 있다. 실험 결과, $H_{2}O_{2}\;:\; H_{2}SO_{4}$ 용액을 사용한 친수성 용액 처리의 경우에 있어서는 수산화기가 3474 $cm^{-1}$ 주위의 넓은 영역에서 관찰되었다. 그러나, diluted HF 용액의 경우에 있어서는 수산화기가 관찰되지 않았다. 접합된 실리콘웨이퍼를 tetramethylammonium hydroxide 식각 용액을 사용하여 식각 공정을 수행하였다. 식각 공정은 자동 식각 중지가 수행되었으며, 식각된 표면은 평탄하고 균일하였다. 그러므로, 이러한 SDB 기술은 우수한 특성을 가진 압력, 유속, 가속도 센서 등과 같은 센서의 제작 및 센서 응용 분야에 이용될 수 있을 것이다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.3310-3312
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• 1999

We have studied the method of silicon direct bonding using the mixture of $HNO_$, $H_2O_2$, and HF chemicals called the controlled slight etch (CSE) solution for the effective wafer cleaning. CSE, two combinations of oxidizing and etching agents, have been used to clean the silicon surfaces prior to wafer bonding. Two wafers of silicon and silicon dioxide were contacted each other at room temperature and postannealed at $300{\sim}1100^{\circ}C$ in $N_2$ ambient for 2.5 h. We have cleaned silicon wafers with the various HF concentrations and characterized the parameters with regard to surface roughness, chemical nature, chemical oxide thickness, and bonding energy. It was observed that the chemical oxide thickness on silicon wafer decreased with increasing HF concentrations. The initial interfacial energy and final energy postannealed at $1100^{\circ}C$ for 2.5h measured by the crack propagation method was 122 $mJ/m^2$ and 2.96 $mJ/m^2$, respectively.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 추계학술대회 논문집
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• pp.81-84
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• 1995

A reliable bonding between two silicon wafers, regularly grooved and non-grooved, was done by the direct boning technology, It is Presented that high structural duality was realized not only at the bended interface but in the bulk, commensurate with the filling of artificial grooves, which would be attributed to the dislocation-gettering capability of groove free-surfaces during annealing. The groove filling would be explained with mass-transport phenomena assisted by the dislocation movement from initial contact boundaries toward groove surfaces. Intrinsic voids can be easily removed by aid of the grooves. The proposed method yielded also an intimate bonding not only between {111} wafers strongly misoriented and slightly inclined to {111} basal plane but even between {111} and {100} orientation wafers.

• Transactions on Electrical and Electronic Materials
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• 제1권1호
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• pp.6-11
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• 2000

The hydrogen plasma treatment of silicon wafers in the reactive ion-etching mode was studied for the application to silicon-on-insulator wafers which were prepared using the wafer bonding technique. The chemical reactions of hydrogen plasma with surface were used for both surface activation and removal of surface contaminants. As a result of exposure of silicon wafers to the plasma, an active oxide layer was found on the surface. This layer was rendered hydrophilic. The surface roughness and morphology were examined as functions of the plasma exposing time and power. In addition, the surface became smoother with the shorter plasma exposing time and power. The value of initial surface energy estimated by the crack propagation method was 506 mJ/㎡, which was up to about three times higher as compared to the case of conventional direct using the wet RCA cleaning method.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.759-762
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• 2000

Present transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area, consequently have disadvantage for high speed switching performance. In this paper, a horizontal structure transistor which has minimized parasitic capacitance in virtue of SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics were designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance was proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed horizontal structure transistor was certified through the VCE-lC characteristics curve, $h_{FE}$ -IC characteristics, and GP-plot.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.3279-3281
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• 1999

This paper describes a method of direct wafer bonding using surfaces activated by a radio-frequency hydrogen plasma. The hydrogen plasma cleaning of silicon in the RIE mode was investigated as a pretreatment for silicon direct bonding. The cleaned silicon surface was successfully terminated by hydrogen, The hydrogen-terminated surfaces were rendered hydrophilic, which could be wetted by Dl water rinse. Two wafers of silicon and silicon dioxide were contacted to each other at room temperature and postannealed at $300{\sim}1100^{\circ}C$ in an $N_2$ atmosphere for 2 h. From the AFM results, it was revealed that the surface became rougher with the increased plasma exposure time and power. The effect of the plasma treatment on the surface chemistry was investigated by the AES analysis. It was shown that the carbon contamination at the surface could be reduced below 5 at %. The interfacial energy measured by the crack propagation method was 122 $mJ/m^2$ and 384 $mJ/m^2$ for RCA cleaning and hydrogen plasm, respectively.

• 천문학회보
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• 제36권2호
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• pp.125.2-125.2
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• 2011

We are developing medium resolution cross-dispersed silicon grisms in the near IR region ($1.45{\sim}5.2{\mu}m$). The grisms will be installed in MIMIR, a multifunction instrument at the Lowel Observatory, USA. The two devices are designed to cover H and K band and L and M band simultaneously. Our goal is to make grism with R=3000 at 1.2 arcsec slit. The Silicon has high refractive index (n=3.4 at $1.5{\mu}m$) which enhances the resolving power by up to 5 times when compared to conventional material such as BK-7 (n=1.5 at 1.5 ${\mu}m$). The bonded grisms will be installed in a filter wheel for the uses switch from spectroscopic mode to imaging mode easily. Our device is compact and light weighted while it provides a decent resolving power. We produce monolithic grisms using e-beam lithography at the NASA JPL and chemically etching the grooves on the silicon prisms. Moreover, the main-disperser and cross-disperser will be contacted together by direct Si-Si bonding technique and eventually turn into one piece. The bonded pair offers more stability in terms of the layout of the spectrum and removes the Fresnel loss at the intersection of two grisms. We report on the proper wafer bonding steps through this research, and inspected the bonding quality thermally, optically and mechanically.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2001년도 춘계학술대회논문집E
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• pp.169-174
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• 2001

This paper reports on the development of high aspect ratio structure and 3-D integrated process for MEMS-based micro gas turbines. To manufacture high aspect ratio structures, Deep Reactive Ion Etching (DRIE) process have been developed and optimized. Specially, in this study, structures with aspect ratios greater than 10 were fabricated. Also, wafer direct bonding and Infra-Red (IR) camera bonding inspection systems have been developed. Moreover, using glass/silicon wafer direct bonding, we optimized the 3-D integrated process.

• 한국표면공학회지
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• 제33권2호
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• pp.101-106
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• 2000

SOI (Silicon-On-Insulator) substrates were fabricated with varying annealing temperature of $25-660^{\circ}C$ by a linear annealing method, which was modified RTA process using a linear shape heat source. The annealing method was applied to Si ∥ $SiO_2$/Si pair pre-contacted at room temperature after wet cleaning process. The bonding strength of SOI substrates was measured by two methods of Razor-blade crack opening and direct tensile test. The fractured surfaces after direct tensile test were also investigated by the optical microscope as well as $\alpha$-STEP gauge. The interface bonding energy was 1140mJ/m$^2$ at the annealing temperature of $430^{\circ}C$. The fracture strength was about 21MPa at the temperature of $430^{\circ}C$. These mechanical properties were not reported with the conventional furnace annealing or rapid thermal annealing method at the temperature below $500^{\circ}C$. Our results imply that the bonded wafer pair could endure CMP (Chemo-Mechanical Polishing) or Lapping process without debonding, fracture or dopant redistribution.

• 한국재료학회지
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• 제16권10호
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• pp.652-655
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• 2006

A direct wafer bonding process necessary for GaAs-on-insulator (GOI) fabrication with high thermal annealing temperatures was studied by using PECVD oxides between gallium arsenide and silicon wafers. In order to apply some uniform pressure on initially-bonded wafer pairs, a graphite sample holder was used for wafer bonding. Also, a tool for measuring the tensile forces was fabricated to measure the wafer bonding strengths of both initially-bonded and thermally-annealed samples. GaAs/$SiO_2$/Si wafers with 0.5-$\mu$m-thick PECVD oxides were annealed from $100^{\circ}C\;to\;600^{\circ}C$. Maximum bonding strengths of about 84 N were obtained in the annealing temperature range of $400{\sim}500^{\circ}C$. The bonded wafers were not separated up to $600^{\circ}C$. As a result, the GOI wafers with high annealing temperatures were demonstrated for the first time.