• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.887-890
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• 2008

We present 2D slab silicon-based photonic crystal optical insulator to enhance light emission efficiency of light-emitting diode (LED). A 2D slab silicon photonic crystal is designed in such a way that light emitting diode die can be placed in the middle of the silicon photonic crystal. The device creates light propagation forbidden region in horizontal plane for Transverse Electric (TE) light with the wavelength range of 450 nm to 600 nm.

• 한국결정성장학회지
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• 제23권3호
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• pp.119-123
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• 2013

Most of the world's solar cells in photovoltaic industry are currently fabricated using crystalline silicon. Czochralski-grown silicon crystals are more expensive than multicrystalline silicon crystals. The future of solar-grade Czochralski-grown silicon crystals crucially depends on whether it is usable for the mass-production of high-efficiency solar cells or not. It is generally believed that the main obstacle for making solar-grade Czochralski-grown silicon crystals a perfect high-efficiency solar cell material is presently light-induced degradation problem. In this work, the substitution of boron with gallium in p-type silicon single crystal is studied as an alternative to reduce the extent of lifetime degradation. The diamond-wire sawing technology is employed to slice the silicon ingot. In this paper, the quality of the diamond wire-sawn gallium-doped silicon wafers is studied from the chemical, electrical and structural points of view. It is found that the characteristic of gallium-doped silicon wafers including texturing behavior and surface metallic impurities are same as that of conventional boron-doped Czochralski crystals.

• 한국결정성장학회지
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• 제11권3호
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• pp.89-95
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• 2001

규소 결정의 용융 온도 근처인 $1350^{\circ}C$에서 Ar과 $O_{2}$gas를 이용하여 규소 wafer의 열처리시 vacancy ty[e 결함의 거동에 대해 알아보았다. 이 열처리에서는 wafer의 표면보다 wafer내부에서 결함의 용해속도가 매우 높음을 확인하였다. 이는 $1350^{\circ}C$에서는 규소내의 평형산소농도가 대부분의 CZ silicon에서의 산소농도보다 높아 산소의 understaturation현상과 silicon interstitial농도의 영향에 기인된 것으로 예상된다. 열처리 분위기의 영향을 알아보기 위하여 Ar과 $O_{2}$ 분위기에서 열처리한 결과 vacancy type 결함의 용해속도는 wafer의 내부에서는 차이가 없었고, wafer의 표면에서는 Ar이 $O_{2}$의 경우보다 결함의 용해속도가 높았다. $O_{2}$의 경우에는 표면산화막 성장시 유입된 silicon interstitial의 농도가 높아 결함의 용해속도가 떨어지는 것으로 판단된다. 이는 기존 연구에서 예상된 silicon interstitial이 vacancy cluster로 알려진 결정결함의 제거에 기여한다는 예상과는 상반된다. 본 연구의 결과 silicon interstitial의 존재는 void외부 산화막의 용해속도를 늦추어 결함 용해속도를 떨어뜨리는 것으로 예상된다.

• 한국결정성장학회지
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• 제1권1호
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• pp.66-73
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• 1991

During the growth of macroscopically dislocation-free Czochralski silicon crystal, micro precipitates causing stacking faults in the silicon wafer during the oxidation are formed Thermal history the cryscausing acquire during the growth process is known to be a key factor determining the nucleation of this micro precipitates. In this article, various mechanisms suggested on the formation of microdefects in the silicon crystal are reviewed to secure the nucleation mechanism of the micro precipitates causing OSF whose pattern is normally ring or annular in CZ silicon crytal. B-defects which are known as vacancy clustering are considered to be the heterogeneous nucleation sites for the micro precipitates causing OSF in the CZ silicon crystals.

• 한국결정성장학회지
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• 제18권4호
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• pp.137-139
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• 2008

Floating zone, neutron transmutation-doped and magnetic Czochralski silicon crystals are being widely used for fabrication power devices. To improve the quality of these devices and to decrease their production cost, it is necessary to use large-diameter wafers with high and uniform resistivity. Recent developments in the crystal growth technology of Czochralski silicon have enable to produce Czochralski silicon wafers with sufficient resistivity and with well-controlled, suitable concentration of oxygen. In addition, using Czoehralski silicon for substrate materials may offer economical benefits, First, Czoehralski silicon wafers might be cheaper than standard floating zone silicon wafers, Second, Czoehralski wafers are available up to diameter of 300 mm. Thus, very large area devices could be manufactured, which would entail significant saving in the costs, In this work, the conventional Czochralski silicon crystals were grown with higher oxygen concentrations using high pure polysilicon crystals. The silicon wafers were annealed by several steps in order to obtain saturated oxygen precipitation. In those wafers high resistivity over $5,000{\Omega}$ cm is kept even after thermal donor formation annealing.

• 한국결정성장학회지
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• 제4권2호
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• pp.111-118
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• 1994

Crystal growth chamber 상부에 있는 reservoir에서 polycrystalline silicon powder를 연속적으로 feeding하면서 도가니 하부에 용융대를 형성시키고 seed를 meed를 dipping하여 회전시키면서 하부로 끌어내려 단결정을 성장시키는 연속성장법의 기본 원리를 확립하였고, 직접 고안 설계 제작한 연속성장 장치로 silicon 단결정을 성장시켰다. 본 연속성장법은 melt에 미치는 중력, 진동, melt의 표면장력, melt와 solid의 계면 장력, seed의 회전에 따른 원심력 등의 힘들이서로 상쇄되고 power, feeding양과 성장속도가 비례하여 적당한 조합을 이룰 때 안정한 연속성장을 할 수있다.

• 한국결정성장학회지
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• 제15권4호
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• pp.129-134
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• 2005

초크랄스키 단결정장치내 실리콘 유동의 자기장효과에 대한 수치해석을 하였다. 8" 단결정 성장과정에서 난류 모형을 사용하여 수송현상을 계산하였다. 도가니 회전수가 작으면 자연대류가 지배적이었다. 도가니 회전수가 증가할수록 강제대류가 증가되며 온도 분포는 더 넓어진다. cusp 자기장을 인가하면 도가니근처의 유동이 크게 감소하며 온도분포는 전도의 경우와 비슷해진다.

• 한국전기전자재료학회논문지
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• 제16권4호
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• pp.292-297
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• 2003

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

• 센서학회지
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• 제22권5호
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• pp.369-373
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• 2013

In this paper, we developed contact type temperature sensor with single crystal silicon strip thermopile. This sensor consists of 15 p-type single crystal silicon strips, 17 n-types and contact electrodes on silicon dioxide silicon membrane. The result of electromotive force measuring showed very good characteristic as $15.18mV/^{\circ}C$ when temperature difference between the two ends of the thermopile occurs by applying thermal contact on the thermopile which was fabricated with silicon strip of $200{\mu}m$ length, $20{\mu}m$ width, $1{\mu}m$ thickness.

• Current Photovoltaic Research
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• 제8권1호
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• pp.17-26
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• 2020

It is clear that monocrystalline Silicon (Si) ingots are the key raw material for semiconductors devices. In the present industries markets, most of monocrystalline Silicon (Si) ingots are made by Czochralski Process due to their advantages with low production cost and the big crystal diameters in comparison with other manufacturing process such as Float-Zone technique. However, the disadvantage of Czochralski Process is the presence of impurities such as oxygen or carbon from the quartz and graphite crucible which later will resulted in defects and then lowering the efficiency of Si wafer. The heat transfer plays an important role in the formation of Si ingots. However, the heat transfer generates convection in Si molten state which induces the defects in Si crystal. In this study, a crystal growth simulation software was used to optimize the Si crystal growth process. The furnace and system design were modified. The results showed the melt-crystal interface shape can affect the Si crystal growth rate and defect points. In this study, the defect points and desired interface shape were controlled by specific crystal growth rate condition.