• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.434-435
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• 2009

The crystalline silicon solar cell where the solar cell market grows rapidly is occupying of about 85% or more. high-efficiency and low cost endeavors many crystalline silicon solar cells. the fabrication processes of high-efficiency crystalline silicon solar cells necessitate complicated fabrication processes and Ti/Pd/Ag contact, however, this contact formation processed by expensive materials. Ni/Cu contact formation is good alternative. in this paper, according to temperature Ni silicide makes, produced Ni/Cu contact solar cell and measured conversion efficiency.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.95-96
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• 2009

A fully depleted capacitorless 1-transistor dynamic random access memory (FD 1T-DRAM) based on a sSOI strained-silicon-on-insulator) wafer was investigated. The fabricated device showed excellent electrical characteristics of transistor such as low leakage current, low subthreshold swing, large on/off current ratio, and high electron mobility. The FD sSOI 1T-DRAM can be operated as memory device by the floating body effect when the substrate bias of -15 V is applied, and the FD sSOI 1T-DRAM showed large sensing margin and several milli seconds data retention time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.05a
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• pp.172-176
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• 1995

Schemes to trap weakly absorbed light into the cell have played an important role in improving the efficiency of both amorphous and crystlline silicon solar cells. One class of scheme relies on randomizing the direction of light within the cell by use of Lambertian(diffuse)surfaces. A second class of scheme relies on the use fo well defined geometrical features to control the direction of light wihin the cell, Widly used geometrical features in crystalline silicon solar cells are the square based pyramids and V-shaped grooves formed in (100) orientated surfaces by intersecting(III) crystallographic planes exposed by anisotropic etching. 18.5% conversion efficiency of Buried Contact Solar Cell with pyramidally textured surface has been achieved. 18.5% efficiency of silicon solar cell is one the highest record in the world The efficieny of cell without textured surface was 16.6%, When adapting textured surface to the Cell, the efficiency has been improved over 12%.

• Journal of the Korean institute of surface engineering
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• v.17 no.2
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• pp.29-40
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• 1984

The structure of rapidly solidified Al-Si-based alloys and its relationship to subsequent anodic film growth in near neutral and acid solutions have been investigated. Solidification of the alloys proceeds via pre-dendritic nuclei, associated with rugosity of the casting surface, from which cellular-type growth, comprised of aluminium-rich material surrounded by silicon-containing material, emanates. Observation of ultramicrotomed sections of the alloys and their anodic films reveals the local oxidation of the silicon-rich phase and its incorporation into the anodic alumina film, formed in near neutral solutions. Such incorporation occurs but resultant isolation of the silicon-rich phase is not possible for anodizing in phosphoric acid, and a three-dimensional network of the oxidized silicon-containing phase, with continuing development of porous anodic alumina, is observed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.5
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• pp.359-363
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• 2011

To integrate the sensor driver and logic circuits, fabricating down scaled transistors has been main issue. At this research, short channel effects were analyzed after n channel polycrystalline silicon thin film transistor was fabricated at high temperature. As a result, on current, on/off current ratio and transconductance were increased but threshold voltage, electron mobility and s-slope were reduced with a decrease of channel length. When carriers that develop at grain boundary in activated polycrystalline silicon have no gate biased, on current was increased with punch through by drain current. Also, due to BJT effect (parallel bipolar effect) that developed under region of channel by increase of gate voltage on current was rapidly increased.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.2
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• pp.130-138
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• 2006

We have investigated pattern scaling down of silicon stamps through the oxidation technique, During oxidizing the silicon stamps, silicon dioxide that has 300 nm and 500 nm thickness was grown, and critical deformations were not observed in the patterns. There was positive effect to reduce size of patterns because vertical and horizontal patterns have different orientation. We achieved pattern reduction rate of $26\%$. In addition, the formation of polymer patterns had been investigated with varied temperature and pressure conditions to improve the filling characteristics of polymers during nanoimprint lithography when pattern sizes were few micrometers. In these varied conditions, polymers had been affected by free space compensation and elastic stress relaxation for filling the cavities. Based on the results, defect control which is an important issue in the nanoimprint lithography were facilitated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.1054-1056
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• 2002

High temperature Kermal diffusion from $POCl_3$ source usually used for conventional process through put of a cell manufacturing line and potentially reduce cell efficiency through bulk like time degradation. To fabricate high efficiency solar cells with minimal thermal processing, spin-on-doping(SOD) technique can be employed to emitter diffusion of a silicon solar cell. A technique is presented to emitter doping of a mono-crystalline solar cell using spin-on doping (SOD). Moreover it is shown that the sheet resistance variation with RTA temperature and time fer mono-crystalline and multi-crystalline silicon samples. This novel SOD technique was successfully used to produces 11.3% efficiency l04mm by 104mm size mono-crystalline silicon solar cells.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.59-60
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• 2006

The slurry stability and removal rate during recycling of slurry in silicon wafer polishing was studied. Average abrasive size of slurry was not changed with recycling time, however, large particles appeared as recycling time increased. Large particles were related foreign substances from pad or abraded silicon flakes during polishing. The removal rate as well as pH of slurry was decreased as recycling time increased. It suggests that the consumption of OH ions during recycling is the main cause of decrease of removal rate. Therefore, it is important to control pH of slurry to obtain optimum removal rate during polishing.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.234-234
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• 2010

Most high efficiency silicon solar cells use a passivated selective emitter. It have been an important research subject for crystalline silicon solar cells for decades. It is being used in production for high efficiency solar cells. Most of the selective emitter process require expensive extra masking, etching steps, and a double diffusion process making selective emitters not cost effective. In this paper, we study method for single diffusion step selective emitter process as an alternative to not cost effective double diffusion process. Cost effective selective emitter that the efficiency should be increased significantly (mare than 0.2%) and that the process should simple, robust and cheap.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.249-249
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• 2010

We investigated novel surface treatment and its impact on silicon photovoltaic cells. Using 2-step etching methods, we have changed the nanostructure on pyramid surface so that less light is reflected. This work proposes an improved texturing technique of mono crystalline silicon surface for solar cells with sub-nanotexturing process. The nanotextured silicon surface exhibits a lower average reflectivity (~4%) in the wavelength range of 300-1100nm without antireflection coating layer. It is worth mentioning that the surface of pyramids may also affect the surface reflectance and carrier lifetime. In one word, we believe nanotextruing is a promising guide for texturization of monocrystalline silicon surface.