• 제목/요약/키워드: Signal processing circuit

검색결과 370건 처리시간 0.029초

Investigating the Effects of Hearing Loss and Hearing Aid Digital Delay on Sound-Induced Flash Illusion

  • Moradi, Vahid;Kheirkhah, Kiana;Farahani, Saeid;Kavianpour, Iman
    • Journal of Audiology & Otology
    • /
    • 제24권4호
    • /
    • pp.174-179
    • /
    • 2020
  • Background and Objectives: The integration of auditory-visual speech information improves speech perception; however, if the auditory system input is disrupted due to hearing loss, auditory and visual inputs cannot be fully integrated. Additionally, temporal coincidence of auditory and visual input is a significantly important factor in integrating the input of these two senses. Time delayed acoustic pathway caused by the signal passing through digital signal processing. Therefore, this study aimed to investigate the effects of hearing loss and hearing aid digital delay circuit on sound-induced flash illusion. Subjects and Methods: A total of 13 adults with normal hearing, 13 with mild to moderate hearing loss, and 13 with moderate to severe hearing loss were enrolled in this study. Subsequently, the sound-induced flash illusion test was conducted, and the results were analyzed. Results: The results showed that hearing aid digital delay and hearing loss had no detrimental effect on sound-induced flash illusion. Conclusions: Transmission velocity and neural transduction rate of the auditory inputs decreased in patients with hearing loss. Hence, the integrating auditory and visual sensory cannot be combined completely. Although the transmission rate of the auditory sense input was approximately normal when the hearing aid was prescribed. Thus, it can be concluded that the processing delay in the hearing aid circuit is insufficient to disrupt the integration of auditory and visual information.

용량형 지문인식센서를 위한 전하분할 방식 감지회로의 CMOS 구현 (A CMOS integrated circuit design of charge-sharing scheme for a capacitive fingerprint sensor)

  • 남진문;이문기
    • 센서학회지
    • /
    • 제14권1호
    • /
    • pp.28-32
    • /
    • 2005
  • In this paper, a CMOS integrated detection circuit for capacitive type fingerprint sensor signal processing is described. We designed a detection circuit of charge-sharing sensing scheme. The proposed detection circuit increases the voltage difference between a ridge and valley. The test chip is composed of $160{\times}192$ array sensing cells (12 by $12.7{\;}mm^{2}$). The chip was fabricated on a 0.35 m standard CMOS process. Measured difference voltage between a ridge and valley was 0.95 V.

센서 신호 처리를 위한 온도 보상 기능을 가진 2단 CMOS 연산 증폭기 (A 2-stage CMOS operational amplifier with temperature compensation function for sensor signal processing)

  • 하상민;서상호;신장규
    • 센서학회지
    • /
    • 제18권4호
    • /
    • pp.280-285
    • /
    • 2009
  • In this paper, we designed a 2-stage CMOS operational amplifier with temperature compensation function using 2-poly 4-metal 0.35 $\mu$m standard CMOS technology. Using two bias circuits, the positive temperature coefficient(PTC) and the negative temperature coefficient(NTC) of the bias circuit are canceled out each other. When reference current circuit is simulated that it has a temperature coefficient of -150 ppm/$^{\circ}C$ with a temperature change from 0 $^{\circ}C$ to 120 $^{\circ}C$. Also the proposed circuit has a temperature coefficient of -0.011 dB/$^{\circ}C$ of DC open loop gain with the same temperature range.

Test Generation for Speed-Independent Asynchronous Circuits with Undetectable Faults Identification

  • Eunjung Oh;Lee, Dong-Ik;Park, Ho-Yong
    • 대한전자공학회:학술대회논문집
    • /
    • 대한전자공학회 2000년도 ITC-CSCC -1
    • /
    • pp.359-362
    • /
    • 2000
  • In this paper, we propose a test pattern generation algorithm on the basis of the identification of undetectable faults for Speed-Independent(SI) asynchronous control circuits. The proposed methodology generates tests from the specification of a target circuit, which describes the behavior of the circuit in the form of Signal Transition Graph (STG). The proposed identification method uses only topological information of a target circuit and reachability information of a fault-free circuit, which is generated in the form of Binary Decision Diagram(BDD) during pre-processing. Experimental results show that high fault coverage over single input stuck-at fault model is obtained for several synthesized SI circuits and the use of the identification process as a preprocessing decreases execution time of the proposed test generation with negligible costs.

  • PDF

호흡 검출 시스템을 위한 초소형 센서 인터페이스 회로 (Miniaturized Sensor Interface Circuit for Respiration Detection System)

  • Jo, Sung-Hun
    • 한국정보통신학회논문지
    • /
    • 제25권8호
    • /
    • pp.1130-1133
    • /
    • 2021
  • In this paper, a miniaturized sensor interface circuit for the respiration detection system is proposed. Respiratory diagnosis is one of the main ways to predict various diseases. The proposed system consists of respiration detection sensor, temperature sensor, and interface circuits. Electrochemical type gas sensor using solid electrolytes is adopted for respiration detection. Proposed system performs sensing, amplification, analog-to-digital conversion, digital signal processing, and i2c communication. And also proposed system has a small form factor and low-cost characteristics through optimization and miniaturization of the circuit structure. Moreover, technique for sensor degradation compensation is introduced to obtain high accuracy. The size of proposed system is about 1.36 cm2.

Energy Efficient Wireless Sensor Networks Using Linear-Programming Optimization of the Communication Schedule

  • Tabus, Vlad;Moltchanov, Dmitri;Koucheryavy, Yevgeni;Tabus, Ioan;Astola, Jaakko
    • Journal of Communications and Networks
    • /
    • 제17권2호
    • /
    • pp.184-197
    • /
    • 2015
  • This paper builds on a recent method, chain routing with even energy consumption (CREEC), for designing a wireless sensor network with chain topology and for scheduling the communication to ensure even average energy consumption in the network. In here a new suboptimal design is proposed and compared with the CREEC design. The chain topology in CREEC is reconfigured after each group of n converge-casts with the goal of making the energy consumption along the new paths between the nodes in the chain as even as possible. The new method described in this paper designs a single near-optimal Hamiltonian circuit, used to obtain multiple chains having only the terminal nodes different at different converge-casts. The advantage of the new scheme is that for the whole life of the network most of the communication takes place between same pairs of nodes, therefore keeping topology reconfigurations at a minimum. The optimal scheduling of the communication between the network and base station in order to maximize network lifetime, given the chosen minimum length circuit, becomes a simple linear programming problem which needs to be solved only once, at the initialization stage. The maximum lifetime obtained when using any combination of chains is shown to be upper bounded by the solution of a suitable linear programming problem. The upper bounds show that the proposed method provides near-optimal solutions for several wireless sensor network parameter sets.

신호 검증을 통한 고속 다층 인쇄회로기판의 설계 (A Design of a High-Speed Multilayer Printed Circuit Board though signal Verification)

  • 최철용
    • 한국정보처리학회논문지
    • /
    • 제5권1호
    • /
    • pp.249-257
    • /
    • 1998
  • 다층 인쇄회로기판에서 고속 신호를 정확하고 신속하게 배선 설계하려면, 물리적 설계 규칙과 신호 잡음을 고려한 전기적 설계 규칙을 정립하고, 적용할 신호 검증 도구를 사용하여 신호의 충실성을 검증하여야 한다. 본 논문은 현재 개발 제작되어 동작 중에 있는 HIPSS(High Performance Storage System)보드에 대한 전기적 설계 규칙과 고속 신호의 배선에 따른 일부 고속 신호의 신호 검증 방법을 설명한다. 또한 전기적 설계 규칙을 적용하여 인쇄회로기판을 설계하는 경우, 발생하는 신호 지연, 반사 그리고 누화 등의 신호 잡음을 검증 도구를 이용하여 시뮬레이션 하고, 분석한 결과를 보이며, 수정된 고속 신호의 배선 설계를 확인한다.

  • PDF

PCB 회로의 신호통합 시뮬레이터 구현에 관한 연구 (A Study on Implementation for Signal Integrity Simulator of the PCB Circuits)

  • 김현호;이천희
    • 한국정보처리학회:학술대회논문집
    • /
    • 한국정보처리학회 2001년도 춘계학술발표논문집 (하)
    • /
    • pp.1209-1212
    • /
    • 2001
  • 본 논문에서는 PCB(Printed Circuit Board)회로에서 고속 신호들을 전달하는 배선의 특성 및 배선의 요구사항에 의한 설계 규칙과 이론화된 공식은 이용하여 PCB상에 배치되는 부품들간의 배선경로를 추적하여 해당 배선의 특성을 분석하고, 흐르는 신호의 특성 및 해당 신호의 전기/전자적인 시뮬레이션을 수행할 수 있도록 하는 PCB회로의 신호통합 시뮬레이터에 대하여 언급하고 실험을 통하여 시뮬레이션의 타당성을 검증하였다.

  • PDF

GIS내부의 부분방전신호 감도개선 및 주파수변환기법에 의한 GIS UHF Sensor 모듈의 외부노이즈차폐기법에 관한 연구 (A Study of the Method for External Noise Shielding using the GIS UHF Sensor Module Applied to the Partial Discharge Signal Sensitivity and Method of Frequency Transforming in the Internal GIS)

  • 이승민
    • 전기학회논문지
    • /
    • 제59권4호
    • /
    • pp.728-732
    • /
    • 2010
  • GIS(Gas insulated switching gear) is power equipment with excellent dielectric strength and is economy merit in high confidence and stability. Recently, because equipment of GIS was occurring problem of confidence used for a long time, partial discharge on-line diagnosis systems have been importantly recognized. Partial discharge (PD) detection is an effective means for monitoring and evaluation of dielectric condition of gas insulated system (GIS). The ultra-high-frequency (UHF) PD detection technique can detect and locate the PD sources inside GIS by detecting electromagnetic wave emitted from PD source. Therefore, real-time diagnostic system using UHF detection method has been developed for this application is being expanded gradually. However, the signal of partial discharge occurring in SF6 gas is very weak and susceptible to external noises which mainly consist of PD in air. Thus, it is important to distinguish the PD in SF6 gas more sensitively from the external noises. Unfortunately, these external noise signals and the partial discharge signals have very similar characteristics. Therefore, to solve this problem, we need the signal processing method for distinguish partial discharge signals with external noise signals for improvement of SNR(signal to noise ratio) and sensitivity. In this paper, we proposed internal signal processing method for removing external noise signals with built-in pre.amplifier and frequency conversion circuit.

무구속 건강모니터링을 위한 심탄도 계측 시스템 구현 및 평가 (Implementation and evaluation of the BCG measurement system for non-constrained health monitoring)

  • 노윤홍;정도운
    • 센서학회지
    • /
    • 제19권1호
    • /
    • pp.8-16
    • /
    • 2010
  • This research proposes measuring of BCG(ballistocardiogram) to monitor heart activities in a non-constrained environment, at home or work. Unlike with ECG, measuring BCG does not require the attachment of leads on the subject's body and allows signal measuring in a non-constrained state. It enables effective long-term monitoring of cardiac conditions. In this study a chair type BCG measurement system to continuous monitor the activity of the heart is implemented. The instrument consists of upper petal and ready for press of chair load cell sensor is attached to measure the change of the object's weight. In order to extract the output ballistic signal from the weight and force sensor signals. Beside the signal processing circuit for the digital conversion, the ballistic signal is detected using DAQ equipment. Signal processing algorithm including wavelet transforms for noise cancellation, template matching for normalization and peak detection in BCG is developed. ECG and BCG were concurrently measured to evaluate the performance of the system, and comparing the characteristics of the two signals verified the possibility of the system in non-constrained and nonconscious health monitoring.