• Journal of Drive and Control
• /
• v.18 no.1
• /
• pp.9-16
• /
• 2021

Overloaded vehicles increase the maintenance cost of road structures, and they are a major factor in causing damage to the roads and bridges. In addition, overloaded vehicles compromise the braking capability of the vehicle; thus, threatening the safety of the driver. In order to prevent overloading of vehicles, the government is cracking down on the roads by using a device that measures the weight of vehicles. But this process is inconvenient because the place where the equipment is installed is far away from where the cargo is loaded. Due to the limitations of these fixed weighing devices, there is a growing need for technology that can monitor vehicle weight distribution and overload conditions in real time. In this work, we develop an onboard scale that can measure the load (weight) of trucks in real time. The onboard scale consists of high sensors, a signal processing unit, and a display, and it measures the load using height-displacement of the vehicle's leaf spring suspension.

• Journal of Astronomy and Space Sciences
• /
• v.38 no.1
• /
• pp.55-63
• /
• 2021

The universe is well known to be consists of dark energy, dark matter and the standard model (SM) particles. The dark matter dominates the density of matter in the universe. The dark matter is thought to be linked with dark photon which are hypothetical hidden sector particles similar to photons in electromagnetism but potentially proposed as force carriers. Due to the extremely small cross-section of dark matter, a large amount of data is needed to be processed. Therefore, we need to optimize the central processing unit (CPU) time. In this work, using MadGraph5 as a simulation tool kit, we examined the CPU time, and cross-section of dark matter at the electron-positron collider considering three parameters including the center of mass energy, dark photon mass, and coupling constant. The signal process pertained to a dark photon, which couples only to heavy leptons. We only dealt with the case of dark photon decaying into two muons. We used the simplified model which covers dark matter particles and dark photon particles as well as the SM particles. To compare the CPU time of simulation, one or more cores of the KISTI-5 supercomputer of Nurion Knights Landing and Skylake and a local Linux machine were used. Our results can help optimize high-energy physics software through high-performance computing and enable the users to incorporate parallel processing.

• Journal of Drive and Control
• /
• v.20 no.4
• /
• pp.17-26
• /
• 2023

A forklift is an industrial vehicle that lifts or transports heavy objects using a hydraulically operated fork, and is equipped with an automatic transmission for the convenience of repetitive transportation, loading, and unloading work. The Transmission Control Unit (TCU) is a key component in charge of the shift control function of an automatic transmission. It consists of an electric circuit with an input/output signal interface function and firmware running on a microcontroller. To develop TCU firmware, the development process of shifting algorithm design, firmware programming, verification test, and performance improvement must be repeated. A simulator is a device that simulates a mechanical system having dynamic characteristics in real time and simulates various sensor signals installed in the system. The embedded transmission simulator is a simulator that is embedded in the TCU firmware. information related to the mechanical system that is necessary for TCU normal operation. In this study, an embedded transmission simulator applied to the originally developed forklift TCU firmware was designed and used to verify various forklift shift control algorithms.

• Journal of Satellite, Information and Communications
• /
• v.11 no.4
• /
• pp.1-9
• /
• 2016

This paper was studied in two ways with respect to the information received from the video signal separation technique of PPI Scop radar device. The proposed technique consists in generating an image signal through the video signal separation and synthesis, symbol generation, the residual image signal generation process. This technology can greatly improve the operating convenience with improved ease of discrimination, screen readability for the operator in analyzing radar information. The first proposed method was constructed for high-speed FPGA-based information processing systems for high speed operation stability of the system. The second proposed method was implemented intelligent algorithms and a software algorithm function curve associated resources.This was required to meet the constraints on the radar information, analysis system. Existing radar systems have not the frame data analysis unit image. However, this study was designed to image data stored in the frame-by-frame analysis of radar images with express information MPEG4 video. Key research content is to highlight the key observations expresses the target, the object-specific monitoring information to the positive image processing algorithm and the function curve delays. For high-definition video, high-speed to implement data analysis and expressing a variety of information was applied to the ARM Processor Support in Pro ASIC3.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.7A
• /
• pp.683-694
• /
• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.3
• /
• pp.46-55
• /
• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.11 s.353
• /
• pp.185-191
• /
• 2006

DSRC((Dedicated Short Range Communication) is dedicated short range communication for wireless communications between RSE(Road Side Equipment) and OBE(On-Board Unit) within vehicle moving high speed. In this paper, we implemented 5.8GHz DSRC modem according to Korea TTA(Telecommunication Technology Association) standard and investigated implementation results and design process for SoC(System on a Chip) embedding ARM CPU which control overall signal and process arithmetic work. The SoC is implemented by 0.11um design technology and 480pins EPBGA package. In the implemented SoC ($Jaguar^{TM}$), 5.8GHz DSRC PHY(Physical Layer) modem and MAC are designed and included. For CPU core ARM926EJ-S is embedded, and LCD controller, smart card controller, ethernet MAC, and memory controller are designed as main function.

• Design & Manufacturing
• /
• v.14 no.2
• /
• pp.21-27
• /
• 2020

Recently, LCD (Liquid Crystal Display) has been replaced by OLDE (Organic Light Emitting Diode) in high resolution display industry. In the process of OLDE production, it inspects defective products by sending a signal using a probe during OLED panel inspection. At this time, the cause of the detection of failure is divided into two. One is the self-defect of the OLED panel and the other is the poor contact occurring in the process of contact between the two. The second case is unknown at the time of testing, which increases the time for retesting. To this end, we made a system that can identify in real time whether the probe is in contact during the inspection. A contact probe unit was designed for the system, and a stage system was implemented. An inspection system was constructed through S / W and circuit configuration for actual inspection. Finally, a system that can check contact and non-contact in real time was constructed.

• Journal of the Korean Society of Manufacturing Process Engineers
• /
• v.3 no.4
• /
• pp.73-80
• /
• 2004

A dual purpose robot automation system is developed for both arc welding and spot welding by one robot within a cell. The need for automation of both arc welding and spot welding processes is urgent while the production volume is not so big as to accommodate separate station for the two processes. Also, space is too narrow for separate station to be settled down in the factory. A spot welding robot is chosen and the function for arc welding are implemented in-house at cost of advanced functions. For the spot welding, a single pole type gun is used and the robot has to push down the plate to be welded, which causes the robot positioning error. Therefore, position error compensation algorithm is developed. The basic functions for the arc welding processes are implemented using the digital I/O board of robot controller, PLC, and A/D conversion PCB. The weaving pattern is taught in meticulously by manual teach. A fixture unit is also developed for dual purpose. The main aspects of the system is presented in this paper especially in the design and implementation procedure. The signal diagrams and sequence logic diagrams are also included. The outcome of the dual purpose welding cell is the increased productivity and good production stability which is indispensable for production volume prediction. Also, it leads to reduction of manufacturing lead time.

• Journal of Sensor Science and Technology
• /
• v.3 no.3
• /
• pp.28-35
• /
• 1994

Caustic Soda Treatment Systems need a concentration measurement device in order to monitor the weight reduction amount of polyester fabrics. Since the reduction process requires several concentration measurements, we have to do the unit titration fast and exactly. Therefore, a proposition of estimation algorithm for finding the equivalent point in the titration process is needed. In this paper, we used the cardinal spline algorithm, to estimate the proper curve with the measured pH-values after each injection of titration sdution, to predict the equivalent point. While the processing time is elapsed, several equivalent points are estimated and drawed the line graph of fabrics weight reduction automatically. Finally, we designed the hardware and the software of an automatic titration system that can generate the reduction ending signal of Caustic Soda Treatment System.