• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.10
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• pp.1-7
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• 2020

In recent years, as LED display systems are actively spread, study on effective control methods for an LED driver for driving the systems has been in progress. The most representative among them is the uniform brightness control method for the LED driver channel. In this paper, we propose an LED driver IC for BLU with current compensation and system protection functions to minimize channel luminance deviation. It is designed for current accuracy within ±3% between channels and a channel current of 150 mA. In order to satisfy the design specifications, the channel amplifier offset was canceled out by a chopping operation using a channel-driving PWM signal. Also, a pre-charge function was implemented to minimize the fast operation speed and luminance deviation between channels. LED error (open, short), switch TR short detection, and operating temperature protection circuits were designed to protect the IC and BLU systems. The proposed IC was fabricated using a Magnachip 0.35-um CMOS process and verified using Cadence and Synopsys' Design Tool. The fabricated LED driver IC has current accuracy within ±1.5% between channels and 150-mA channel output characteristics. The error detection circuits were verified by a test board.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.269-274
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• 2013

To proportionally control the electronic valve position of the actuator, we designed and fabricated PCU, CPT, and rotary absolute optical encoder for the detection of absolute angular position in the actuator. We also designed and constructed the test system by using DAQ hardware and Labview. We designed PCU to convert 1-5 V, 0-5 V, 0-10 V, 2-10 V voltage signals and 4-20 mA current signals to the voltage signals in the common 0.5-2.5 V range. We designed CPT to output 4-20 mA current signals corresponding to the valve positions based on the PWM signal input from the MCU. We also designed 20 bit optical encoder by using infrared LED and infrared transistor and made the serial communication with the main board possible. When we tested PCU and CPT with DAQ hardware and Labview software, they operated correctly with the small errors within ${\pm}0.003$ V and ${\pm}0.01$ mA, respectively, showing that our actuator has the excellent performance to employ as the industrial proportional-valve-actuator. The resolution of the encoder was $11.25^{\circ}$ and the maximum revolution to detect was 32,768.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.9
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• pp.1079-1086
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• 2012

In this paper, X-band 60 W Solid-State Power Amplifier with sequential control circuit and pulse width variation circuit for improve bias of SSPA module was designed. The sequential control circuit operate in regular sequence drain bias switching of GaAs FET. The distortion and efficiency of output signals due to SSPA nonlinear degradation is increased by making operate in regular sequence the drain bias wider than that of RF input signals pulse width if only input signal using pulsed width variation. The GaAs FETs are used for the 60 W SSPA module which is consists of 3-stage modules, pre-amplifier stage, driver-amplifier stage and main-power amplifier stage. The main power amplifier stage is implemented with the power combiner, as a balanced amplifier structure, to obtain the power greater than 60 W. The designed SSPA modules has 50 dB gain, pulse period 1 msec, pulse width 100 us, 10 % duty cycle and 60 watts output power in the frequency range of 9.2~9.6 GHz and it can be applied to solid-state pulse compression radar using pulse SSPA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3C
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• pp.302-313
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• 2010

In this paper, we propose an enhanced AGC (Automatic Gain Control) structure and P-SCH detection method for initial cell search in 3GPP (3rdGenerationPartnershipProject) LTE (Long Term Evolution) FDD(Frequency Division Duplex) / TDD (Time Division Duplex) dual mode system. Since TDD frame structure consists of uplink subframe and downlink subframe, conventional AGC structure causes P-SCH detection performance degradation by increase of AGC variation due to signal power difference between uplink and downlink subframe. Also, P-SCH detection performance is degraded by distortion of P-SCH correlation characteristic in frequency offset and multipath fading channel environments. Therefore, we propose an AGC structure which can minimize P-SCH detection performance degradation with stable operation in 3GPP LTE TDD mode as well as FDD mode. Also we propose a P-SCH detection method which can reduce distortion of correlation chareteristics in frequency offset and multipath fading environments and obtain good P-SCH detection performance. Simulation results show that the proposed AGC structure and P-SCH detection method have stable AGC operation and excellent P-SCH detection performance for 3GPP LTE TDD / FDD dual mode downlink receiver in various channel environments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• The Korean Journal of Pharmacology
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• v.29 no.1
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• pp.97-105
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• 1993

Adenosine receptors in rat adipose tissues have been reported to be of $A_{1}$ subclass, and their stimulation leads to inhibition of adenylyl cyclase, resulting in inhibition of lipolysis. In the present study we investigated changes in $A_{1}$ adenosine receptor-adenylyl cyclase system of adipocytes following induction of experimental diabetes in rats. One week following experimental diabetes were induced by intravenous injection of streptozotocin (50 mg/kg body wt.), adipocytes from rats $(170{\sim}230g)$ fed ad libitum were isolated using collagenase. When adipocytes were incubated for 1 h with 1 unit/ml adenosine deaminase and $1\;{\mu}M$ isoproterenol, and assayed for glycerol formation, it was found that the inhibition of lipolysis in diabetic adipocytes by $(-)-N^{6}-(R-phenylisopropyl)adenosine$ (PIA), an $A_{1}$, adenosine receptor agonist, was twice that of control adipocytes. In an effort to delineate the mechanism(s), $[^{3}H]PIA$ binding to adipocytic membranes from diabetic and control rats were determined. Neither the affinities nor numbers of $A_{1}$ adenosine receptor were significantly different from each other (Best fit parameters for the one-site model are: $K_{d}=0.51{\pm}0.09nM$ and $B_{max}=1.60{\pm}0.12\;pmoles/mg$ protein for control membranes; $K_{d}=0.54{\pm}0.21\;nM$ and $B_{max}=1.72{\pm}0.31\;pmoles/mg$ protein for diabetic membranes). However, the inhibiton by PIA of the isoproterenol-stimulated adenylyl cyclase activities was found to be 1.9 times higher in adipocytic membranes from diabetic rats than those from controls. These results suggest that the increased sensitivity of inhibition of lipolysis to PIA in adipocytic membranes from diabetic rats is due to changes in signal transduction pathways, rather than alterations of $A_{1}4 adenosine receptor molecules themselves.

• Journal of Korean Society of Transportation
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• v.22 no.3 s.74
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• pp.145-157
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• 2004

The cycle length design model of the Korean traffic responsive signal control systems is devised to vary a cycle length as a response to changes in traffic demand in real time by utilizing parameters specified by a system operator and such field information as degrees of saturation of through phases. Since no explicit guideline is provided to a system operator, the system tends to include ambiguity in terms of the system optimization. In addition, the cycle lengths produced by the existing model have yet been verified if they are comparable to the ones minimizing delay. This paper presents the studies conducted (1) to find shortcomings embedded in the existing model by comparing the cycle lengths produced by the model against the ones minimizing delay and (2) to propose a new direction to design a cycle length minimizing delay and excluding such operator oriented parameters. It was found from the study that the cycle lengths from the existing model fail to minimize delay and promote intersection operational conditions to be unsatisfied when traffic volume is low, due to the feature of the changed target operational volume-to-capacity ratio embedded in the model. The 64 different neural network based cycle length design models were developed based on simulation data surrogating field data. The CORSIM optimal cycle lengths minimizing delay were found through the COST software developed for the study. COST searches for the CORSIM optimal cycle length minimizing delay with a heuristic searching method, a hybrid genetic algorithm. Among 64 models, the best one producing cycle lengths close enough to the optimal was selected through statistical tests. It was found from the verification test that the best model designs a cycle length as similar pattern to the ones minimizing delay. The cycle lengths from the proposed model are comparable to the ones from TRANSYT-7F.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1210-1230
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• 1997

In this paper, we suggest an architecture of DS/CDMA tranceiver composed of one pilot channel used as reference and multiple traffic channels. The pilot channel-an unmodulated PN code-is used as the reference signal for synchronization of PN code and data demondulation. The coherent demodulation architecture is also exploited for the reverse link as well as for the forward link. Here are the characteristics of the suggested DS/CDMA system. First, we suggest an interlaced quadrature spreading(IQS) method. In this method, the PN coe for I-phase 1st channel is used for Q-phase 2nd channels and the PN code for Q-phase 1st channel is used for I-phase 2nd channel, and so on-which is quite different from the eisting spreading schemes of DS/CDMA systems, such as IS-95 digital CDMA cellular or W-CDMA for PCS. By doing IQS spreading, we can drastically reduce the zero crossing rate of the RF signals. Second, we introduce an adaptive threshold setting for the synchronization of PN code, an initial acquistion method that uses a single PN code generator and reduces the acquistion time by a half compared the existing ones, and exploit the state machines to reduce the reacquistion time Third, various kinds of functions, such as automatic frequency control(AFC), automatic level control(ALC), bit-error-rate(BER) estimator, and spectral shaping for reducing the adjacent channel interference, are introduced to improve the system performance. Fourth, we designed and implemented the DS/CDMA MODEM to be used for variable transmission rate applications-from 16Kbps to 1.024Mbps. We developed and confirmed the DS/CDMA MODEM architecture through mathematical analysis and various kind of simulations. The ASIC design was done using VHDL coding and synthesis. To cope with several different kinds of applications, we developed transmitter and receiver ASICs separately. While a single transmitter or receiver ASC contains three channels (one for the pilot and the others for the traffic channels), by combining several transmitter ASICs, we can expand the number of channels up to 64. The ASICs are now under use for implementing a line-of-sight (LOS) radio equipment.

• Journal of Navigation and Port Research
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• v.38 no.4
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• pp.373-378
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• 2014

In order to prepare for recapitalization of differential GNSS (DGNSS) reference station and integrity monitor (RSIM) due to GNSS diversification, this paper focuses on differential correction algorithm using GPS/Galileo pesudorange. The technical standards on operation and broadcast of DGNSS RSIM are described as operation of differential GPS (DGPS) RSIM for conversion of DGNSS RSIM. Usually, in order to get the differential corrections of GNSS pesudorange, the system must know the real positions of satellites and user. Therefore, for calculating the position of Galileo satellites correctly, using the equation for calculating the SV position in Galileo ICD (Interface Control Document), it estimates the SV position based on Ephemeris data obtained from user receiver, and calculates the clock offset of satellite and user receiver, system time offset between GPS and Galileo, then determines the pseudorange corrections of GPS/Galileo. Based on a platform for performance verification connected with GPS/Galileo integrated signal simulator, it compared the PRC (pseudorange correction) errors of GPS and Galileo, analyzed the position errors of DGPS, DGalileo, and DGPS/DGalileo respectively. The proposed method was evaluated according to PRC errors and position accuracy at the simulation platform. When using the DGPS/DGalileo corrections, this paper could confirm that the results met the performance requirements of the RTCM.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.5
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• pp.94-104
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• 2000

The accuracy and reliability of the target tracking is very critical issue in the design of automotive collision warning radar A significant problem in multi-target tracking (MTT) is the target-to-measurement data association If an incorrect measurement is associated with a target, the target could diverge the track and be prematurely terminated or cause other targets to also diverge the track. Most methods for target-to-measurement data association tend to coalesce neighboring targets Therefore, many algorithms have been developed to solve this data association problem. In this paper, a new multi-target data association method based on order statistics is described The new approaches. called the order statistics probabilistic data association (OSPDA) and the order statistics joint probabilistic data association (OSJPDA), are formulated using the association probabilities of the probabilistic data association (PDA) and the joint probabilistic data association (JPDA) filters, respectively Using the decision logic. an optimal or near optimal target-to-measurement data association is made A computer simulation of the proposed method in a heavy cluttered condition is given, including a comparison With the nearest-neighbor CNN). the PDA, and the JPDA filters, Simulation results show that the performances of the OSPDA filter and the OSJPDA filter are superior to those of the PDA filter and the JPDA filter in terms of tracking accuracy about 18% and 19%, respectively In addition, the proposed method is implemented using a developed digital signal processing (DSP) board which can be interfaced with the engine control unit (ECU) of car engine and with the d?xer through the controller area network (CAN)