• Journal of the Korean Operations Research and Management Science Society
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• v.24 no.2
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• pp.69-80
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• 1999

A genetic algorithm to determine the optimal signal sequence and double cycle pattern is described. The signal sequence and double cycle pattern are used as the input for TRANSYT to find optimal signal timing at each junction in the area traffic networks, In the genetic process, the partially matched crossover and simple crossover operators are used for evolution of signal sequence and double cycle pattern respectively. A special conversion algorithm is devised to convert the signal sequence into the link-stage assignment for TRANSYT. Results from tests using data from an area traffic network in Leicester region R are given.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2164-2170
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• 2010

Digital Radio Frequency Memory, ( as DRFM ), is a device with the ability to restore output to the input RF signal in the required time after storing the incoming RF signals. Therefore DRFM is widely used in Jammer, EW Simulator, Target Echo Generator, and so on. This paper proposes its hardware implementation composed with the high frequency part and the digital processing part consisting of RF input/output module and local oscillator module. It is also proposed the replicated signal generation method which is consisted of the Analog-Digital conversion in the form of pulsed RF signal quantization, and FPGA to save and produce the playback signal, and RF signals to produce a Digital-Analog Conversion in the digital processing unit. This proposed scheme applied to test board and confirmed the validity of the proposed scheme through the test results obtained by the simulated input signals.

• Journal of Satellite, Information and Communications
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• v.1 no.1
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• pp.59-64
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• 2006

The broadband power detector for power amplitude envelope detection of the direct-conversion Six-port output signal was designed and implemented in this paper. The power detector should be linearly operated to produce the linear amplitude and phase signal for input RF signals in required broadband frequency range. The power detector should be designed under conditions of matching circuit with low VSWR, which protect unbalanced phase signal from reflection signal due to mismatch between the output port of a six-port and the input port of a power detector. The designed power detectors, which were implemented in L-band with 50 ohm matching and Ku-band with multiple LC matching circuits and isolator, respectively, were analyzed in viewpoints of the utilization as a power detector of direct conversion Six-port. The dynamic range of designed power detectors were also measured and rvaluated as a power detector of Six-port circuit.

• Smart Structures and Systems
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• v.32 no.4
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• pp.253-266
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• 2023

The time-reversal method is employed to improve the ability of pipeline defect detection, and a new approach of identifying the pipeline defect depth is proposed in this research. When the L(0,2) mode ultrasonic guided wave excited through a lead zirconate titinate (PZT) transduce array propagates along the pipeline with a defect, it will interact with the defect and be partially converted to flexural F(n, m) modes and longitudinal L(0,1) mode. Using a receiving PZT array attached axisymmetrically around the pipeline, the L(0,2) reflection signal as well as the mode conversion signals at the defect are obtained. An appropriate rectangle window is used to intercept the L(0,2) reflection signal and the mode conversion signals from the obtained direct detection signals. The intercepted signals are time reversed and re-excited in the pipeline again, result in the guided wave energy focusing on the pipeline defect, the L(0,2) reflection and the L(0,1) mode conversion signals being enhanced to a higher level, especially for the small defect in the early crack stage. Besides the L(0,2) reflection signal, the L(0,1) mode conversion signal also contains useful pipeline defect information. It is possible to identify the pipeline defect depth by monitoring the variation trend of L(0,2) and L(0,1) reflection coefficients. The finite element method (FEM) simulation and experiment results are given in the paper, the enhancement of pipeline defect reflection signals by time-reversal method is obvious, and the way to identify pipeline defect depth is demonstrated to be effective.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.1
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• pp.150-158
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• 2010

Filtering is necessary for the SRC(sample rate converter), that is used to change the sampling rate of a digital signal. The larger the conversion ratio of the sampling rate becomes, the more signal processing is needed for the filter, which means more complexity on realization. Thus it is important to reduce the amount of signal processing for the case of substantial conversion ratios. In this paper it is presented an efficient design method of a multistage FIR(finite impulse response) filter, with which the rate conversion occurs in stages rather than in one step. In this method, filter searching is performed exhaustively over all possible factorization of the conversion ratio, and also the filter complexity is measured based on direct realization rather than on estimation. It has been shown a designed multistage filter to have a less number of multiplications for filtering operation in comparison with a conventionally designed one. It has also been found that by allowing some variations of the filter architecture such as a halfband filter or a filter with multiple transition bands, the number of multiplications can be reduced further.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.5
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• pp.1071-1077
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• 2010

The six-port phase correlator using lumped elements was designed and fabricated in this paper, also the receiving performance of L-band direct conversion receiver using lumped six-port phase correlator element was analyzed. The proposed L-band lumped six-port phase correlator element was composed of a resistive power divider and the twist-wire coaxial cables. The proposed lumped six-port structure provides the small-sized configuration and wide-band characteristics. The performance of the L-band lumped direct conversion receiver structure was measured under the conditions of 1.69 GHz frequency for LO-CW signal and RF-QPSK signal, which are input signals for the lumped six-port phase correlator element. The direct conversion receiving structure using the proposed lumped six-port phase correlator element can recovered the good digital I/Q signal.

• Phonetics and Speech Sciences
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• v.12 no.3
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• pp.55-63
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• 2020

Voice conversion can be applied to various voice processing applications. It can also play an important role in data augmentation for speech recognition. The conventional method uses the architecture of voice conversion with speech synthesis, with Mel filter bank as the main parameter. Mel filter bank is well-suited for quick computation of neural networks but cannot be converted into a high-quality waveform without the aid of a vocoder. Further, it is not effective in terms of obtaining data for speech recognition. In this paper, we focus on performing voice-to-voice conversion using only the raw spectrum. We propose a deep learning model based on the transformer network, which quickly learns the voice conversion properties using an attention mechanism between source and target spectral components. The experiments were performed on TIDIGITS data, a series of numbers spoken by an English speaker. The conversion voices were evaluated for naturalness and similarity using mean opinion score (MOS) obtained from 30 participants. Our final results yielded 3.52±0.22 for naturalness and 3.89±0.19 for similarity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.4
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• pp.668-675
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• 2001

Recently, the performance of the commercial PCS(Personal Communication Service) system has been improved to the uppermost limit and ultimately the next generation mobile communication is to be realized by IMT-2000 (International Mobile Communication-2000) to provide multimedia services. Therefore, the new type receiving system is researched actively and one of the most important part in a receiver is direct conversion method. The direct conversion method is suitable for low power consumption, small size, MMIC, and low price, which is to be adopted to the next generation mobile communication systems. In this case, however, several problems occur due to DC-offset. The DC-offset suppresses amplification of the required signal because of the leakage signal of frequency synthesizer in the system. In this thesis, the removing method of DC-offset was considered. There are four removing techniques of DC-offset, which are AC-coupling, large capacitor, DC-feedback loop, and DC-free coding. Among these, the AC-coupling method is the most simplest method and the DC-feedback loop method has the best performance. Then, the performance of the AC-coupling method and DC-feedback loop method are evaluated by HP's ADS simulation tool. As a result, the AC-coupling method cannot be used to the digital communication systems due to data loss. On the other hand, it was confirmed that the DC-feedback loop method is suitable for the direct conversion receiver.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.7
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.104-107
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• 2000

We designed and implemented the RFIC(RF front-end IC) for DTV(Digital TV) tuner. The DTV tuner RF front-end consists of low noise IF amplifier fur the amplification of 900 MHz RF signal and down conversion mixer for the RF signal to 44MHz IF conversion. The RFIC is implemented on ETRI 0.8u high resistive (2㎘ -cm) and evaluated by on wafer, packaged chip test. The gain and IIP3 of IF amplifier are 15㏈ and -6.6㏈m respectively. For the down conversion mixer gain and IIP3 are 13㏈ and -6.5㏈m. Operating voltage of the IF amplifier and the down mixer is 5V, current consumption are 13㎃ and 26㎃ respectively.