• 한국전기전자재료학회논문지
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• 제22권4호
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• pp.342-349
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• 2009

This study investigated the growth characteristics of carbon nanotubes (CNTs) by changing a period of annealing time and a $C_{2}H_{2}/H_2$ flow ratio at temperature as low as $450^{\circ}C$ with inductively coupled plasma chemical vapor deposition. The 1-nm-thick Fe-Ni-Co alloy thin film served as a catalyst layer for the growth of CNTs, which was thermally evaporated on the 15-nm-thick Al underlayer deposited on the 50-nm-thick Ti diffusion barrier. The annealing at low temperature of $450^{\circ}C$ brought about almost no granulation of the catalyst layer, and the CNT growth was not affected by a period of annealing time. A study of changing the flow rate of $C_{2}H_{2}$ and $H_2$ showed that as the ratio of the $C_{2}H_{2}$ flow rate to the $H_2$ flow rate was lowered, the CNTs were grown to be longer With further decreasing the flow ratio, the length of CNTs reached the maximum and then became shorter. Under the optimized gas flow rates, we successfully synthesized CNTs with a uniform length over a 4-inch Si wafer at $450^{\circ}C$.

• 한국재료학회지
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• 제19권1호
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• pp.33-36
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• 2009

Inorganic-organic composite thin-film-transistors (TFTs) of ZnO nanowire/Poly(3-hexylthiophene) (P3HT) were investigated by changing the nanowire densities inside the composites. Crystalline ZnO nanowires were synthesized via an aqueous solution method at a low temperature, and the nanowire densities inside the composites were controlled by changing the ultrasonifiaction time. The channel layers were prepared with composites by spin-coating at 2000 rpm, which was followed by annealing in a vacuum at $100^{\circ}C$ for 10 hours. Au/inorganic-organic composite layer/$SiO_2$ structures were fabricated and the mobility, $I_{on}/I_{off}$ ratio, and threshold voltage were then measured to analyze the electrical characteristics of the channel layer. Compared with a P3HT TFT, the electrical properties of TFT were found to be improved after increasing the nanowire density inside the composites. The mobility of the P3HT TFT was approximately $10^{-4}cm^2/V{\cdot}s$. However, the mobility of the ZnO nanowire/P3HT composite TFT was increased by two orders compared to that of the P3HT TFT. In terms of the $I_{on}/I_{off}$ ratio, the composite device showed a two-fold increase compared to that of the P3HT TFT.

• The Korean Journal of Ceramics
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• 제3권4호
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• pp.274-278
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• 1997

(Ba, Sr) TiO$_3$(BST) thin films were prepared on RuO$_2$/Si substrates by rf magnetron sputtering and annealing was followed at temperatures ranging from 550 to 80$0^{\circ}C$ in $N_2$or $O_2$atmosphere. The effects of annealing conditions on the properties of BST film deposited on RuO$_2$bottom electrodes were investigated. It was found that the crystallinity. surface roughness, and grain size of BST films vary with the annealing temperature but they are not dependent upon the annealing atmosphere. The flat region in the current-voltage (I-V) curves of BST capacitors shortened with increasing annealing temperature under both atmospheres. This is believed to be due to the lowering of potential barrier caused by unstable interface and the increase of charge The shortening of the flat region by $O_2$annealing was more severe than that by $N_2$-annealing. As a result, there was no flat region when the films were annealed at 700 and 80$0^{\circ}C$ in $O_2$atmosphere. The dielectric properties of BST films were improved by annealing in either atmosphere. however, a degradation with frequency was observed when the films were annealed at relatively high temperature under $O_2$atmosphere.

• 한국재료학회지
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• 제23권2호
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• pp.116-122
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• 2013

For fabricating silicon solar cells with high conversion efficiency, texturing is one of the most effective techniques to increase short circuit current by enhancing light trapping. In this study, four different types of textures, large V-groove, large U-groove, small V-groove, and small U-groove, were prepared by a wet etching process. Silicon substrates with V-grooves were fabricated by an anisotropic etching process using a KOH solution mixed with isopropyl alcohol (IPA), and the size of the V-grooves was controlled by varying the concentration of IPA. The isotropic etching process following anisotropic etching resulted in U-grooves and the isotropic etching time was determined to obtain U-grooves with an opening angle of approximately $60^{\circ}$. The results indicated that U-grooves had a larger diffuse reflectance than V-grooves and the reflectances of small grooves was slightly higher than those of large grooves depending on the size of the grooves. Then amorphous Si:H thin film solar cells were fabricated on textured substrates to investigate the light trapping effect of textures with different shapes and sizes. Among the textures fabricated in this work, the solar cells on the substrate with small U-grooves had the largest short circuit current, 19.20 mA/$cm^2$. External quantum efficiency data also demonstrated that the small, U-shape textures are more effective for light trapping than large, V-shape textures.

• Advances in Energy Research
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• 제1권2호
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• pp.97-106
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• 2013

This study designs and tests a photovoltaic system with distributed maximum power point tracking (DMPPT) methodology using a field programmable gate array (FPGA) controller. Each solar panel in the distributed PV system is equipped with a newly designed DC/DC converter and the panel's voltage output is regulated by a FPGA controller using PI control. Power from each solar panel on the system is optimized by another controller where the quadratic maximization MPPT algorithm is used to ensure the panel's output power is always maximized. Experiments are carried out at atmospheric insolation with partial shading conditions using 4 amorphous silicon thin film solar panels of 2 different grades fabricated by Chi-Mei Energy. It is found that distributed MPPT requires only 100ms to find the maximum power point of the system. Compared with the traditional centralized PV (CPV) system, the distributed PV (DPV) system harvests more than 4% of solar energy in atmospheric weather condition, and 22% in average under 19% partial shading of one solar panel in the system. Test results for a 1.84 kW rated system composed by 8 poly-Si PV panels using another DC/DC converter design also confirm that the proposed system can be easily implemented into a larger PV power system. Additionally, the use of NI sbRIO-9642 FPGA-based controller is capable of controlling over 16 sets of PV modules, and a number of controllers can cooperate via the network if needed.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.187-187
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• 2012

In this report, the plasmonic nanopores of less than 5 nm diameter were fabricated on the apex of the pyramidal cavity array. The metallic pyramidal pit cavity can also utilized as the plasmonic bioreactor, and the fabricated Au or Al metallic nanopore can provide the controllable translocation speed down using the plasmonic optical force. Initially, the SiO2 nanopore on the pyramidal pit cavity were fabricated using conventional microfabrication techniques. Then, the metallic thin film was sputter-deposited, followed by surface modification of the nanometer thick membrane using FESEM, TEM and EPMA. The huge electron intensity of FESEM with ~microsecond scan speed can provide the rapid solid phase surface transformation. However, the moderate electron beam intensity from the normal TEM without high speed scanning can only provide the liquid phase surface modification. After metal deposition, the 100 nm diameter aperture using FIB beam drilling was obtained in order to obtain the uniform nano-aperture. Then, the nanometer size aperture was reduced down to ~50 nm using electron beam surface modification using high speed scanning FESEM. The followed EPMA electron beam exposure without high speed scanning presents the reduction of the nanosize aperture down to 10 nm. During these processes, the widening or the shrinking of the nanometer pore was observed depending upon the electron beam intensity. Finally, using 200 keV TEM, the diameter of the nanopore was successively down from 10 nm down to 1.5 nm.

• 마이크로전자및패키징학회지
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• 제18권1호
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• pp.23-27
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• 2011

전기화학적 에칭을 이용한 다공성 실리콘 이중층 형성은 초박형 태양전지 제작에서 PS layer transfer 기술을 적용하기 위한 선행 공정이다. 다공성 실리콘 층의 다공도는 전류밀도와 에칭용액 내 불산의 농도를 조절하여 제어할 수 있다. 전기화학적 에칭을 이용한 다공성 실리콘 형성을 위하여 비저항 $0.01-0.02\;{\Omega}{\cdot}cm$의 p-type (100)의 실리콘 웨이퍼를 사용하였으며, 에칭용액의 조성은 HF (40%) : $C_2H_5OH$(99 %) : $H_2O$ = 1 : 1 : 2 (volume)으로 고정하였다. PS layer transfer 기술에 사용되는 다공성 실리콘 이중층을 형성하기 위해서 에칭 도중 전류밀도를 낮은 전류밀도 조건에서 높은 전류밀도 조건으로 변환하여 low porosity layer 하부에 high porosity layer를 형성할 수 있다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.124-125
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• 2007

Single crystal $CdGa_2Se_4$ layers were grown on a thoroughly etched semi-insulating GaAs(100) substrate at $420^{\circ}C$ with the hot wall epitaxy (HWE) system by evaporating the polycrystal source of $CdGa_2Se_4$ at $630^{\circ}C$ prepared from horizontal electric furnace. The photocurrent and the absorption spectra of $CdGa_2Se_4$/SI(Semi-Insulated) GaAs(100) are measured ranging from 293K to 10K. The temperature dependence of the energy band gap of the $CdGa_2Se_4$, obtained from the absorption spectra was well described by the Varshni's relation, $E_g$(T) = 2.6400 eV - $(7.721{\times}10^{-4}\;eV/K)T^2$/(T + 399 K). Using the photocurrent spectra and the Hopfield quasicubic model, the crystal field energy$({\Delta}cr)$ and the spin-orbit splitting energy$({\Delta}so)$ for the valence band of the $CdGa_2Se_4$ have been estimated to be 106.5 meV and 418.9 meV at 10 K, respectively. The three photocurrent peaks observed at 10 K are ascribed to the $A_{1^-},\;B_{1^-},\;and\;C_{11^-}$ exciton peaks.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.273.2-273.2
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• 2014

Sputtering process has been widely used in Si-based semiconductor industry and it is also an ideal method to deposit transparent oxide materials for thin-film transistors (TFTs). The oxide films grown at low temperature by conventional RF sputtering process are typically amorphous state with low density including a large number of defects such as dangling bonds and oxygen vacancies. Those play a crucial role in the electron conduction in transparent electrode, while those are the origin of instability of semiconducting channel in oxide TFTs due to electron trapping. Therefore, post treatments such as high temperature annealing process have been commonly progressed to obtain high reliability and good stability. In this work, the scheme of electron-assisted RF sputtering process for high quality transparent oxide films was suggested. Through the additional electron supply into the plasma during sputtering process, the working pressure could be kept below $5{\times}10-4Torr$. Therefore, both the mean free path and the mobility of sputtered atoms were increased and the well ordered and the highly dense microstructure could be obtained compared to those of conventional sputtering condition. In this work, the physical properties of transparent oxide films such as conducting indium tin oxide and semiconducting indium gallium zinc oxide films grown by electron-assisted sputtering process will be discussed in detail. Those films showed the high conductivity and the high mobility without additional post annealing process. In addition, oxide TFT characteristics based on IGZO channel and ITO electrode will be shown.

• 한국재료학회지
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• 제4권5호
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• pp.510-515
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• 1994

플라즈마 화학 증착법으로 (100)p-type Si wafer위에 $Y_2O_3$-Stabilzed $ZrO_2$박막을 증착하였다. 반응 기체로는 zirconium triflouracethylacetonate[Zr(tfacac) $[Zr(tfacac)_4]$, tri(2.2.6.6 tetramethy1-3, 5-heptanate) yttrium $[Y(DPM)_3]$과 oxygen gas를 사용하였다. X-ray diffraction(XRD)과 fourier Particle induced x-ray emission(PIXE)을 통하여 $Y(DPM)_3$ bubbling temperature가 $160^{\circ}C, 165^{\circ}C, 170^{\circ}C$일때 $Y_2O_3$함량이 12.1mo1%, 20.4mol%, 31.6mol%임을 알 수 있었다. C-V측정에서 $Y(DPM)_3$ bubbling temperature가 증가함에 따라 flat band voltage가 더욱더 음의 방향으로 이동하였다.