• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.305-305
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• 2010

It is known that a pulse of electrons of high kinetic energy (1-3 eV) in metals can be generated with the deposition of external energy to the surface such as in the absorption of light or in exothermic chemical processes. These energetic electrons are not in thermal equilibrium with the metal atoms and are called "hot electrons" The concept of photon energy conversion to hot electron flow was suggested by Eric McFarland and Tang who directly measured the photocurrent on gold thin film of metal-semiconductor ($TiO_2$) Schottky diodes [1]. In order to utilize this scheme, we have fabricated metal-semiconductor Schottky diodes that are made of Pt or Au as a metallic layer, Si or $TiO_2$ as a semiconducting substrate. The Pt/$TiO_2$ and Pt/Si Schottky diodes are made by PECVD (Plasma Enhanced Chemical Vapor Deposition) for $SiO_2$, magnetron sputtering process for $TiO_2$, e-beam evaporation for metallic layers. Metal shadow mask is made for device alignment in device fabrication process. We measured photocurrent on Pt/n-Si diodes under AM1.5G. The incident photon to current conversion efficiency (IPCE) at different wavelengths was measured on the diodes. We also show that the steady-state flow of hot electrons generated from photon absorption can be directly probed with $Pt/TiO_2$ Schottky diodes [2]. We will discuss possible approaches to improve the efficiency of photon energy conversion.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.2
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• pp.207-212
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• 2013

A novel pixel circuit that uses only n-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (LTPS-TFTs) to compensate the threshold voltage variation of a OLED driving TFT is proposed. The proposed 6T1C pixel circuit consists of 5 switching TFTs, 1 OLED driving TFT and 1 capacitor. When the threshold voltage of driving TFT varies by ${\pm}0.33$ V, Smartspice simulation results show that the maximum error rate of OLED current is 7.05 % and the error rate of anode voltage of OLED is 0.07 % at Vdata = 5.75 V. Thus, the proposed 6T1C pixel circuit can realize uniform output current with high immunity to the threshold voltage variation of poly-Si TFT.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.10
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• pp.821-825
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• 2009

Recently, transparent ZnO-based TFTs have attracted much attention for flexible displays because they can be fabricated on plastic substrates at low temperature. We report the fabrication and characteristics of ZnO TFTs having different channel thicknesses deposited at low temperature. The ZnO films were deposited as active channel layer on $Si_3N_4/Ti/SiO_2/p-Si$ substrates by RF magnetron sputtering at $100^{\circ}C$ without additional annealing. Also, the ZnO thin films deposited at oxygen partial pressures of 40%. ZnO TFTs using a bottom-gate configuration were investigated. The $Si_3N_4$ film was deposited as gate insulator by PE-CVD at $150^{\circ}C$. All Processes were processed below $150^{\circ}C$ which is optimal temperature for flexible display and were used dry etching method. The fabricated devices have different threshold slop, field effect mobility and subthreshold slop according to channel thickness. This characteristics are related with ZnO crystal properties analyzed with XRD and SPM. Electrical characteristics of 60 nm ZnO TFT (W/L = $20\;{\mu}m/20\;{\mu}m$) exhibited a field-effect mobility of $0.26\;cm^2/Vs$, a threshold voltage of 8.3 V, a subthreshold slop of 2.2 V/decade, and a $I_{ON/OFF}$ ratio of $7.5\times10^2$.

• Journal of Sensor Science and Technology
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• v.6 no.1
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• pp.6-15
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• 1997

This paper presents the multi-objective optimal design of thermopile sensor having beam or membrane structure. The thermopile sensor is composed of $Si_{3}N_{4}/SiO_{2}$ dielectric membrane, Al-polysilicon thermocouples and $RuO_{2}$ thin film for black body. The sensing method is based on the Seebeck effect which is originated from the temperature difference of the two positions, black body and silicon rim. The objective functions of the presented design are sensitivity, detectivity and thermal time constant. The modelling of the sensor is proposed including the package. The multi-objective optimization technique is applied to the design of the sensor not only inspecting the modelling equation but also simulating mathematical programming method. Especially, fuzzy optimization technique is adapted to get the optimal solution which enables the designer to reach the more practical solution. The design constraint of the voltage output originated from the change of the environmental temperature is included for practical use.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.633-636
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• 2003

In this work, We, for the first time, present the effects of the thermal annealing of the W/SiO$_2$ multi-layer quarter wavelength reflectors on the resonant properties of the ZnO-based SMR devices. In order to improve the resonant properties of the SMR devices, we annealed thermally the reflectors formed on a silicon substrate using a RF magnetron sputtering technique. As a result, the resonant properties of the SMR devices were observed to strongly depend on the annealing conditions applied to the reflectors. The SMR devices with the reflectors annealed at 40$0^{\circ}C$/30min showed excellent resonance properties as compared to those with the reflectors non-annealed (as-deposited). The newly proposed simple thermal annealing process will be very useful to more effectively improve the resonant properties of the future SMR devices with W/SiO$_2$ multi-layer quarter wavelength reflectors.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1263-1264
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• 2007

자계 유도 고상결정화(FESPC)를 이용하여 제작한 다결정실리콘(poly-Si) 박막 트랜지스터(TFT)는 비정질 실리콘 박막 트랜지스터(a-Si:H TFT)보다 뛰어난 전기적 특성과 우수한 안정성을 지닌다. $V_{DS}$ = -0.1 V에서 채널 폭과 길이가 각각 $5\;{\mu}m$, $7\;{\mu}m$인 P형 TFT의 이동도(${\mu}$)와 문턱 전압($V_{TH}$)은 각각 $31.98\;cm^2$/Vs, -6.14 V 이다. FESPC TFT는 일반 poly-Si TFT에 비해 채널 내 결정 경계 숫자가 많아서 상대적으로 열악한 특성을 가진다. 채널 길이 $5\;{\mu}m$인 TFT의 $V_{TH}$는 채널 길이 $18\;{\mu}m$ 소자의 $V_{TH}$보다 1.36V 작지만, 일반적으로 큰 값이다. 이 현상은 채널에 다수의 결정 경계가 존재하고, 수평 전계가 크기 때문이다. 수평 전계가 증가하면, 결정 경계의 전위 장벽 높이가 감소하게 되는데, 이는 DIGBL 효과이다. ${\mu}$의 증가에 따라서, 드레인 전류가 증가하고 $V_{TH}$은 감소한다. 활성화 에너지($E_a$)는 드레인 전압과 결정 경계의 수에 따라 변하는데, 드레인 전압이 크거나 결정 경계의 수가 감소하면 $E_a$는 감소한다. $E_a$가 감소하면 $V_{TH}$가 감소한다. 유리기판 위의 FESPC를 이용한 P형 poly-Si TFT의 $V_{TH}$는 채널의 길이와 $V_{DS}$에 영향을 받는다. 증가한 수평 전계가 결정 경계에서 에너지 장벽을 낮추는 효과를 일으키기 때문이다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.8 no.1
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• pp.64-72
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• 1998

In this work, we have investigated the change of surface roughness, grain size and crystallinity of Poly-$Si_{1-x}Ge_x$ films deposited with the variation of deposition parameters (temperature, pressure, Ge composition ) and the effect of these results on the electrical resistivity. The crystallinity and the grain size were increased with increasing deposition temperature and Ge composition. Also, the electrical resistivity was decreased by enhanced grain size, while the surface roughness was increased. With increasing deposition pressure, the crystallinity was increased, but the grain size and the cluster size were decreased, by which the surface roughness was decreased. And the electrical resistivity was increased. Based on the effect of the crystallinity and the grain size on the electrical resistivity, it was founded that the electrical resistivity was depend on the grain size rather than the crystallinity.

• Membrane Journal
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• v.9 no.2
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• pp.97-106
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• 1999

A and 2SM-5 type zeoli tic crystal films were synthesized on porous supports from the reaction mixture of 1.9 ${SiO}_2$1.5 $Na_20-Al_2O_3-40$ $H_20$ and $Si0_2$-0.l3 $Na_2O$-52 $H_20$-O.l2 TPAOH composition, respectively. The zeolite films were characterized by XRD and SEM. The 2SM -5 crystals grown on the porous matrix were very closely bound together. It was so difficult to obtain the perfectly intergrown crystals in the case of A-type zeolite and this crystal was transformed into P-type zeolite membrane with a prolonged reaction time. The densely intergrown A type zeolite crystal membrane could be also synthesized by the hydrothermal treatment at 100$^{\cirt}C$ after pressing the reaction mixture without addition of water. The pervaporation performance of the synthesized porous inorganic membranes was investigated for alcohol and water mixtures. A-type zeolite membrane crystallized as a thin film showed the selective \'Jermeability of water from the mixtures through the molecular sieving activity of micropores.

• Journal of the Korean Vacuum Society
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• v.11 no.3
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• pp.176-182
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• 2002

Amorphous $TiO_2$ thin films were deposited on glass substrates by ion beam sputtering in which the ratio of $O_2$/Ar gas used as discharged gas was varied from 0 to 2. After optical and microstructure properties and chemical composition of thin films was analyzed, antireflection coating layers were fabricated with $SiO_2$/$TiO_2$ multi-layers. Thin films deposition was performed at room temperature and ion beam voltage and ion current density for sputtering of target were fixed at 1.2 kV and 200 $\mu\textrm{A}/\textrm{cm}^2$, respectively. Refractive indexs of the deposited $TiO_2$films were 2.40-2.45 at a wavelength of 633 nm. $TiO_2$films had high transmission and stoichiometry when ratio of $O_2$/Ar was 1. Rms roughness of deposited $TiO_2$ film was below 7 $\AA$. In excessive $O_2$ environments, however Rms roughness increased over 50 $\AA$. Transmittance decreased by scattering of rough surface. Reflectance of $SiO_2$/$TiO_2$multi-layers was below 1% in visible light.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.55-56
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• 2009

Small RFID tag antenna were fabricated on Si substrate and their physical and electrical properties were evaluated. With decreasing the size of tag antenna on Si substrate, small SMD-type RFID tags could be fabricated, which is very useful for PCB tracking. Firstly, tag antenna pattern and the electromagnetic properties were simulated with HFSS. The frequency was 13.56MHz, the line-width and line-gap were modeled in the range of $50{\sim}200{\mu}m$. S parameters, SRF, and Q value were calculated from geometry. When the line-width and line-gap were 100um and the loop-turn was 10, the SRF was 80MHZ and the Q value was ca. 9. When the microstrip antenna pattern of aluminum was fabricated by using DC sputtering, Vpp of ca. 1.6V was obtained when the reader-tag distance was 40mm.