• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.45-50
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• 2020

We investigated the Si_1-xGe_x surface properties when dry cleaning the films using NF₃ / H₂O remote plasma. After the dry cleaning process, it was found that about 80-250 nm wide bumps were formed on the SiGe surface regardless of Ge concentration in the rage of x = 0.1 ~ 0.3. In addition, effects of the dry cleaning processing parameters such as pressure, substrate temperature, and H₂O flow rates were examined. It was found that the surface bump is significantly dependent on the flow rate of H₂O. Based on these observations, we would like to provide additional guidelines for implementing the dry cleaning process to SiGe materials.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1672-1678
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• 1989

Major problems preventing the device-quality GaAs/Si heterostructure are the lattice mismatch of about 4% and difference in thermal expansion coefficient by a factor of 2.64 between Si and GaAs. Ge is a good candidate for the buffer layer because its lattice parameter and thermal expansion coefficient are almost the same as those of GaAs. As a first step toward developing heterostructure such as GaAs/Ge/Si entirely by a home-built PAE (plasma-assisted epitaxy), Ge films have been deposited on p-type Si (100)substrate by the plasma assisted evaporation of solid Ge source. The characteristics of these Ge/Si heterostructure were determined by X-ray diffraction, SEM and Auge electron spectroscope. PAE system has been successfully applied to quality-good Ge layer on Si substrate at relatively low temperature. Furthermore, this system can remove the native oxide(SiO2) on Si substrate with in-situ cleaning procedure. Ge layer grown on Si substrate by PAE at substrate temperature of 450\ulcorner in hydrogen partial pressure of 10mTorr was expected with a good buffer layer for GaAs/Ge/Si heterostructure.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1996.06a
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• pp.422-448
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• 1996

Low-temperature epitaxial growth of Si and SiGe layers of Si is one of the important processes for the fabrication of the high-speed Si-based heterostructure devices such as heterojunction bipolar transistors. Low-temperature growth ensures the abrupt compositional and doping concentration profiles for future novel devices. Especially in SiGe epitaxy, low-temperature growth is a prerequisite for two-dimensional growth mode for the growth of thin, uniform layers. UHV-ECRCVD is a new growth technique for Si and SiGe epilayers and it is possible to grow epilayers at even lower temperatures than conventional CVD's. SiH and GeH and dopant gases are dissociated by an ECR plasma in an ultrahigh vacuum growth chamber. In situ hydrogen plasma cleaning of the Si native oxide before the epitaxial growth is successfully developed in UHV-ECRCVD. Structural quality of the epilayers are examined by reflection high energy electron diffraction, transmission electron microscopy, Nomarski microscope and atomic force microscope. Device-quality Si and SiGe epilayers are successfully grown at temperatures lower than 600℃ after proper optimization of process parameters such as temperature, total pressure, partial pressures of input gases, plasma power, and substrate dc bias. Dopant incorporation and activation for B in Si and SiGe are studied by secondary ion mass spectrometry and spreading resistance profilometry. Silicon p-n homojunction diodes are fabricated from in situ doped Si layers. I-V characteristics of the diodes shows that the ideality factor is 1.2, implying that the low-temperature silicon epilayers grown by UHV-ECRCVD is truly of device-quality.

• Proceedings of the Korean Vacuum Society Conference
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• 1998.02a
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• pp.20-20
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• 1998

I Ion beam technology has recently attracted much interest because it has exciting t technological p아:ential for surface analysis, ion beam mixing, surface cleaning and etching i in thin film growth and semiconductor fabrication processes, etc. Es야~cially, ion beam s sputtering has been widely used for sputter depth profiling with x-photoelectron S spectroscopy (XPS) , Auger electron s$\pi$~troscopy(AES), and secondary-ion mass S야i따oscopy(SIMS). However, The problem of surface compositional ch없1ge due to ion b bombardment remains to be understo여 없ld solved. So far sputtering processes have been s studied by s따face an외ysis tools such as XPS, AES, and SIMS which use the sputtering p process again. It would be improbable to measure the modified surface composition profiles a accurately due to ion beam bombardment with surface analysis techniques based on sputter d depth profiling. However, recently Medium energy ion scattering spectroscopy(MEIS) has b been applied to study the sputtering of solid surface at ion bombardment and has been p proved that it has been extremely valuable in probing the surface composition 뻐d s structure nondestructively and quantita디vely with less than 1.0 nm depth resolution. To u understand the sputtering processes of solid surface at ion bombardment, The Molecular D Dynamics(MD) and Monte Carlo(MC) simulation has been used and give an intimate i insight into the sputtering processes of solid surfaces. In this presentation, the sputtering processes of alloys and compound samples at ion b bombardment will be reviewed and the MEIS results for the Ar+ sputter induced altered l layer of the TazOs thin film 뻐dd없nage profiling of Ar+ ion sputt얹"ed Si(100) surface will b be discussed with the results of MD and MC simulation.tion.