• Bulletin of the Korean Chemical Society
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• v.24 no.7
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• pp.953-956
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• 2003

Hexagonal GaN (h-GaN) films have been grown on Si(111) substrates by metal organic chemical vapor deposition using the azidodiethylgallium methylamine adduct, Et₂Ga(N₃)·NH₂Me, as a new single precursor. Deposition was carried out in the substrate temperature range 385-650 °C. The GaN films obtained were stoichiometric and did not contain any appreciable amounts of carbon impurities. It was also found that the GaN films deposited on Si(111) had the [0001] preferred orientation. The photoluminescence spectrum of a GaN film showed a band edge emission peak characteristic of h-GaN at 378 nm.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.6
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• pp.580-585
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• 2004

Silicon dioxide (SiO$_2$) is widely used as a gate dielectric material for thin film transistors (TFT) and semiconductor devices. In this paper, SiO$_2$ films were grown by APCVD(Atmospheric Pressure chemical vapor deposition) at the high temperature. Experimental investigations were carried out as a function of $O_2$ gas flow ratios from 0 to 200 1pm. This article presents the SiO$_2$ gate dielectric studies in terms of deposition rate, refrative index, FT-IR, C-V for the gate dielectric layer of thin film transistor applications. We also study defect passivation technique for improvement interface or surface properties in thin films. Our passivation technique is Forming Gas Annealing treatment. FGA acts passivation of interface and surface impurity or defects in SiO$_2$ film. We used RTP system for FGA and gained results that reduced surface fixed charge and trap density of midgap value.

• Transactions on Electrical and Electronic Materials
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• v.1 no.2
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• pp.7-11
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• 2000

a-Si:H and poly-Si TFT(thin film transistor) characteristics were investigated using an inverted staggered type TFT. The TFT an as-grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. The poly-Si films were achieved by using an isothermal and RTA treatment for glow discharge deposited a-Si:H films. The a-Si:H films were cystallized at the various temperature from 600$^{\circ}C$ to 1000$^{\circ}C$. As anneal temperature was elevated, the TFT exhibited increased g$\sub$m/ and reduced V$\sub$ds/. V$\sub$T/. The poly-Si grain boundary passivation with grain boundary trap types and activation energies as a function of anneal temperature. The poly-si TFT showed an improved I$\sub$nm//I$\sub$off/ ratio of 10$\^$6/, reduced gate threshold voltage, and increased field effect mobility by three orders.

• Journal of the Korean Vacuum Society
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• v.2 no.4
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• pp.439-454
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• 1993

The phase sequence of codeposited Co-Si alloy and Co/si multilayer thin film was investigated by differential scanning calormetry(DSC) and X-ray diffraction (XRD) analysis, The phase sequence in codeposition and codeposited amorphous Co-Si alloy thin film were CoSilongrightarrow Co2Si and those in Co/Si multilayer thin film were CoSilongrightarrowCo2Silongrightarrow and CoSilongrightarrowCo2Si longrightarrowCoSilongrightarrowCoSi2 with the atomic concentration ration of Co to Si layer being 2:1 and 1:2 respectively. The observed phase sequence was analyzed by the effectvie heat of formatin . The phase determining factor (PDF) considering structural facotr in addition to the effectvie heat of formation was used to explain the difference in the first crystalline phase between codeposition, codeposited amorphous Co-Si alloy thin film and Co/Si multilayer thin film. The crystallinity of Co-silicide deposited by multitarget bias cosputter deposition (MBCD) wasinvestigated as a funcion of deposition temperature and substrate bias voltage by transmission electron microscopy (TEM) and epitaxial CoSi2 layer was grown at $200^{\circ}C$ . Parameters, Ear, $\alpha$(As), were calculate dto quantitatively explain the low temperature epitaxial grpwth of CoSi2 layer. The phase sequence and crystallinity had a stronger dependence on the substrate bias voltage than on the deposition temperature due to the collisional daxcade mixing, in-situ cleannin g, and increase in the number of nucleation sites by ion bombardment of growing surface.

• Journal of the Korean Ceramic Society
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• v.35 no.6
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• pp.535-542
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• 1998

SOI(silicon oninsulator) was fabricated through the direct bonding of a hydrophilized single crystal Si wafer and a thermally oxidized SiO2 thin film to investigate the stacking faults in silicon at the Si/SiO2 in-terface. At first the oxidation kinetics of SiO2 thin film and the stacking fault distribution at the oxidation interface were investigated. The stacking faults could be divided into two groups by their size and the small-er ones were incorporated into the larger ones as the oxidation time and temperature increased. The den-sity of the smaller ones based critically lower eventually. The SOI wafers directly bonded at the room temperature were annealed at 120$0^{\circ}C$ for 1 hour. The stacking faults at the bonding and oxidation interface were examined and there were anomalies in the distributions of the stacking faults of the bonded region to arrange in ordered ring-like fashion.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.8
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• pp.714-719
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• 2005

NiCr thin film was deposited by DC magnetron sputtering on $A;_2O_3$/Si substrate with NiCr (80:20) alloy target. NiCr thin films were annealed at $300^{\circ}C,\;400^{\circ}C,\;500^{\circ}C,\;600^{\circ}C,\;and\;700^{\circ}C$ for 6 hr in $H_2$ after annealing at $500^{\circ}C$ for 6hr in air atmosphere, respectively. To analyze NiCr thin film properties, the changes of its micro structure were Investigated through field emission scanning electron microscope (FESEM). X-ray photoelectron spectroscopy (XPS) was used to analyze a surface of NiCr thin film. Resistance of NiCr thin film was measured by 4-point probe technique. The generated heats were measured by infrared thermometer through the application of DC voltage (5 V/l2 V). NiCr thin film treated by gradational double annealing process had uniform and small grains. Maximum temperature generated heat by NiCr micro heater was $173^{\circ}C$. We expect that our results will be a useful reference in the realization of NiCr micro heater.

• New & Renewable Energy
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• v.2 no.3
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• pp.31-36
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• 2006

Superstrate pin amorphous silicon thin-film(a-Si:H) solar cells are prepared on $SnO_2:F$ and ZnO:Al transparent conducting oxides(TCO) in order to see the effect of TCO/p-layers on a-Si:H solar cell operation. The solar cells prepared on textured ZnO:Al have higher open circuit voltage VOC than cells prepared on $SnO_2:F$. Presence of thin microcrystalline p-type silicon layer(${\mu}c-Si:H$) between ZnO:Al and p a-SiC:H plays a major role by causing improvement in fill factor as well as $V_{OC}$ of a-Si:H solar cells prepared on ZnO:Al TCO. Without any treatment of pi interface, we could obtain high $V_{OC}$ of 994mV while keeping fill factor(72.7%) and short circuit current density $J_{SC}$ at the same level as for the cells on $SnO_2:F$ TCO. This high $V_{OC}$ value can be attributed to modification in the current transport in this region due to creation of a potential barrier.

• 한국신재생에너지학회:학술대회논문집
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• 2006.06a
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• pp.158-161
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• 2006

Superstrate pin amorphous silicon thin-film (a-Si:H) solar cells are prepared on $SnO_2:F$ and ZnO:Al transparent conducting oxides (TCO) In order to see the effect of TCO/P-layers on a-Si:H solar cell operation. The solar cells prepared on textured ZnO:Al have higher open circuit voltage $V_{oc}$ than cells prepared on $SnO_2:F$. Presence of thin microcrystalline p-type silicon layer $({\mu}c-Si:H)$ between ZnO:Al and p a-SiC:H plays a major role by causing improvement in fill factor as well as $V_{oc}$, of a-Si:H solar cells prepared on ZnO:Al TCO. Without any treatment of pi interface, we could obtain high $V_{oc}$, of 994mv while keeping fill factor (72.7%) and short circuit current density $J_{sc}$ at the same level as for the cells on $SnO_2:F$ TCO. This high $V_{oc}$ value can be attributed to modification in the current transport in this region due to creation of a potential barrier.

• Proceedings of the KIEE Conference
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• 1998.11c
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• pp.850-852
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• 1998

SiC thin film have been prepared by ICP-CVD for low temperature deposition and large area deposition. The structural properties of deposited SiC films are characterized by employing SEM, FT-IR, XRD, XPS and Raman Spectroscopy. From the experimetal results, good crystallinity has been achieved in $1000^{\circ}C$ grown SiC film which have carbonization step at $1100^{\circ}C$ for substrate bias of 30V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.3
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• pp.234-240
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• 2001

Using RF magnetron sputtering, amorphous carbon(a-C) thin films as electron filed emitter were fabricated. these a-C thin films were deposited on Si(001) substrate at several temperatures. The field electron emission property of these a-C thin films was estimated by a diode technique. As the result, we observed that the field emission properties of the films were changed singnificantly with the substrate temperature and structural features of a-C film. The field emission properties were promoted by higher substrate temperatures. Furthermore N-doped a-C film exhibits more field emission property than that of undoped a-C film. These results are explained as change of surface morphology and structural properties of a-C film.