• ETRI Journal
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• v.19 no.1
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• pp.26-35
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• 1997

The substrate effects on solid-phase crystallization of amorphous silicon (a-Si) films deposited by low-pressure chemical vapor deposition (LPCVD) using $Si_2H_6$ gas have been extensively investigated. The a-Si films were prepared on various substrates, such as thermally oxidized Si wafer ($SiO_2$/Si), quartz and LPCVD-oxide, and annealed at 600$^{\circ}C$ in an $N_2$ ambient for crystallization. The crystallization behavior was found to be strongly dependent on the substrate even though all the silicon films were deposited in amorphous phase. It was first observed that crystallization in a-Si films deposited on the $SiO_2$/Si starts from the interface between the a-Si and the substrate, so called interface-interface-induced crystallization, while random nucleation process dominates on the other substrates. The different kinetics and mechanism of solid-phase crystallization is attributed to the structural disorderness of a-Si films, which is strongly affected by the surface roughness of the substrates.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.6-6
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• 2010

This paper describes that single crystal cubic silicon (3C-SiC) films have been deposited on carbonized Si(100) substrate using hexamethyldisilane(HMDS, $Si_2(CH_3)_6$) as a safe organosilane single-source precursor and a nonflammable mixture of Ar and $H_2$ gas as the carrier gas by APCVD at $1280^{\circ}C$. The 3C-SiC film had a very good crystal quality without defects due to viods, a very low residual stress.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.69-70
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• 2008

Micro resonators have been actively investigated for bio/chemical sensors and RF M/NEMS devices. Among various materials, SiC is a very promising material for micro/nano resonators since the ratio of its Young's modulus, E, to mass density, $\rho$, is significantly higher than other semiconductor materials, such as, Si and GaAs. Polycrystalline 3C-SiC cantilever with different lengths were fabricated using a surface micromachining technique. Polycrystalline 3C-SiC micro resonators were actuated by piezoelectric element and its fundamental resonance was measured by a laser vibrometer in air and vacuum at room temperature, respectively. For the cantilever with $100{\mu}m$ length, $10{\mu}m$width and $1.3{\mu}m$ thickness, the fundamental frequency appeared at 147.2 kHz.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.577-595
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• 2017

${\bullet}$ Silicon Carbide (SiC) had excellent material properties as the base material for next generation of power semiconductor. In developing SiC MOSFET, gate oxide reliability issues had to be first overcome before commercial application. Besides, a high and stable gate-source voltage threshold $V_{GS(th)}$ is also an important parameter for operation robustness. SiC MOSFET with such characteristics can directly use existing high-speed IGBT gate driver IC's. ${\bullet}$ The linear voltage drop characteristics of SiC MOSFET will bring lower conduction loss averaged over full AC cycle compared to similarly rate IGBT. Lower switching loss enable higher switching frequency. Using package with auxiliary source terminal for gate driving will further reduce switching losses. Dynamic characteristics can fully controlled by simple gate resistors. ${\bullet}$ The low switching losses characteristics of SiC MOSFET can substantially reduce power losses in high switching frequency operation. Significant power loss reduction is also possible even at low switching frequency and low switching speed. in T-type 3-level topology, SiC MOSFET solution enable three times higher switching freqeuncy at same efficiency.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.67-67
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• 2000

CeO2는 cubic 구조의 일종인 CaR2 구조를 가지고 있으며 격자상수가 Si의 격장상수와 매우 비슷하여 Si 기판위에 에피텍셜하게 성장할 수 있는 가능성이 매우 크다. 따라서 SOI(silicon-on-insulator)구조의 실현을 위하여 Si 기판위에 CeO2 박막을 에피텍셜하게 성장시키려는 많은 노력이 있어왔다. 또한 metal-ferroelectric-semiconductor field effect transistor)에서 ferroelectric 박막과 Si 기판사이의 완충층으로 사용된다. 이러한 CeO2의 응용을 위해서는 Si 기판 위에 성장된 CeO2 박막의 방위성 및 CeO2/Si 구조의 전기적 특성을 알아보는 것이 매우 중요하다. 본 연구에서는 Si(100) 기판위에 CeO2(200)방향으로 성장하는 박막과 EcO2(111) 방향으로 성장하는 박막을 rf magnetron sputtering 방법으로 증착하여 각각의 구조적, 전기적 특성을 분석하였다. RCA 방법으로 세정한 P-type Si(100)기판위에 Ce target과 O2를 사용하여 CeO2(200) 및 CeO2(111)박막을 증착하였다. 증착후 RTA(rapid thermal annealing)방법으로 95$0^{\circ}C$, O2 분위기에서 5분간 열처리를 하였다 이렇게 제작된 CeO2 박막의 구조적 특성을 XRD(x-ray diffraction)방법으로 분석하였고, Al/CeO2/Si의 MIS(metal-insulator-semiconductor)구조를 제작하여 C-V (capacitance-voltage), I-V (current-voltage) 특성을 분석하였으며 TEM(transmission electron microscopy)으로 증착된 CeO2막과 Si 기판과의 계면 특성을 연구하였다. C-V특성에 있어서 CeO2(111)/Si은 CeO2(111)의 두께가 증가함에 따라 hysteresis windows가 증가한 방면 CeO2(200)/Si은 hysteresis windows가 아주 작을뿐만 아니라 CeO2(200)의 두께가 증가하더라도 hysteresis windos가 증가하지 않았다. CeO2(111)/Si과 CeO2(200)/Si의 C-V 특성의 차이는 CeO2(111)과 CeO2(200)이 Si 기판에 의해 받은 stress의 차이와 이에 따른 defect형성의 차이에 의한 것으로 사료된다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.112-113
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• 2007

$SiO_2$ 절연 박막위에 희석된 PMMA 유기물을 처리하였다. 유기물 처리량에 따른 $SiO_2$ 박막의 $620{\sim}1100\;cm^{-1}$ 영역의 FTIR 스펙트라를 분석한 결과 0.3~0.7%로 PMMA 처리된 박막에서 친핵성 반응이 밀어나는 것을 확인하였으며, 친핵성 반응이 일어나는 박막들에서 누설전류가 적었으며, 절연특성이 우수한 것을 확인하였다.

• Journal of the Semiconductor & Display Technology
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• v.7 no.1
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• pp.41-45
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• 2008

We studied the electrical characteristics of low-k SiOCR interlayer dielectric(ILD) films fabricated by plasma enhanced chemical vapor deposition (PECVD). The precursor bis-trimethylsilylmethane (BTMSM) was introduced into the reaction chamber with the various flow rates. The absorption intensities of Si-O-$CH_x$, bonding group and Si-$CH_x$, bonding group changed synchronously for the variation of precursor flow rate, but the intensity of Si-O-Si(C) responded asynchronously with the $CH_x$, combined bonds. The SiOCH films revealed ultra low dielectric constant around 2.1(1) and reduced further below 2.0 by heat treatments.

• Journal of the Korean Vacuum Society
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• v.16 no.5
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• pp.348-352
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• 2007

In submicron processes, the feature size of ULSI devices is critical, and it is necessary both to reduce the RC time delay for device speed performance and to enable higher current densities without electromigration. In case of contacts between semiconductor and metal in semiconductor devices, it may be very unstable during the thermal annealing process. To prevent these problems, we deposited tungsten carbon nitride (W-C-N) ternary compound thin film as a diffusion barrier for preventing the interdiffusion between metal and semiconductor. The thickness of W-C-N thin film is $1,000{\AA}$ and the process pressure is 7mTorr during the deposition of thin film. In this work we studied the interface effects W-C-N diffusion barrier using the XRD and 4-point probe.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.3
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• pp.147-152
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• 2019

With the recent emphasis on the importance of energy conservation, studies on high-efficiency elevator systems are being continuously conducted. Therefore, pulse width modulation converters are commonly used in traction drives on elevator systems. Wide bandgap devices have been increasingly commercialized, and their application to power conversion systems, such as renewable and energy storage system, has been gradually increasing. In this study, a SiC inverter for an elevator traction drive is investigated. In particular, an inverter is designed to minimize stray and parasitic inductance. Input and output filters are designed by considering switching frequency. The designed SiC inverter reduces volume by approximately 32% compared with that of a Si inverter, and power converter efficiency is over 98.8%.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1025-1027
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• 2009

Novel low temperature deposition process for nano-crystalline Si thin film is developed with the hyper-thermal neutral beam (HNB) technology. By our HNB assisted CVD system, the reactive particles can induce crystalline phase in Si thin films and effectively combine with heating effect on substrate. At low deposition temperature under $80^{\circ}C$, the HNB with proper incident energy controlled by the reflector bias can effectively enhance the nano-crystalline formation in Si thin film without any additional process. The electrical properties of Si thin films can be varied from a-Si to nc-Si according to change of HNB energy and substrate temperature. Characterization of these thin films with conductivity reveal that crystalline of Si thin film can increase by assist of HNB with appropriate energy during low temperature deposition. And low temperature prcoessed nc-Si TFT performance has on-off ratio as order 5.