• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.433-435
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• 1987

Thermal reoxidation was carried out to eliminate hole traps at the surface of Si wafer. As the result, the good surface state of wafer was obtained and hole traps were eliminate at the inversion layer. For the evaluation of reoxidation effects. MOS diode was fabricated and its C-Y curve was plotted.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1996.06a
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• pp.88-138
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• 1996

Electronics grew up to the largest industry in the world supported by Si wafer. In near future, the Si wafer may use 300mm in diameter for economic requirement. This size wafer may use to produce large logic chip, 256Mbit DRAM, and other large complex and high density chip. Then, the quality including flatness and crustal characters may be required very high performance. And, their price should be reasonable and high quantity may be required. These requirements should be solve lot of hard problems of crystal growth, wafering mechanical processing and their cost problems. In this presentation, I may discuss following items.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.1
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• pp.26-32
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• 2012

Polishing is one of the important methods in manufacturing of Si wafers and in thinning of completed device wafers. This study will report the characteristic of wafer according to processing time, machining speed and pressure which have major influence on the abrasion of Si wafer polishing. It is possible to evaluation of wafer abrasion by load cell and infrared temperature sensor. The characteristic of wafer surface according to processing condition is selected to use a result data that measure a pressure, machining speed, and the processing time. This result is appeared by the characteristic of wafer surface in machining condition. Through that, the study cans evaluation a wafer characteristic in variable machining condition. It is important to obtain optimal condition. Thus the optimum condition selection of ultra precision Si wafer polishing using load cell and infrared temperature sensor. To evaluate each machining factor, use a data through each sensor. That evaluation of abrasion according to variety condition is selected to use a result data that measure a pressure, machining speed, and the processing time. And optimum condition is selected by this result.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.3
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• pp.19-23
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• 2015

In this study, two types of Au/TiW bump samples were fabricated by the electroplating process onto Al/Si and SiN/Si wafers for the COG (Chip On Glass) packaging. TiW was used as the UBM (Under Bump Metallurgy) material of the Au bump and it was deposited by a sputtering method under the sputtering powers ranges from 500 to 5000 Watt. We investigated the delamination phenomenas for the prepared samples as a function of the input sputtering powers. The stable interfacial adhesion condition was found to be 1500 Watt in sputtering power. In addition, the SAICAS (Surface And Interfacial Cutting Analysis System) measurement was used to find the adhesion strength of Au bumps for the prepared samples. TiW UBM films were deposited at the 1500 Watt sputtering power. As a results, there was a similar adhesion strengths between TiW/Au interfacial films on Al/Si and SiN/Si wafers. However, the adhesion strength of TiW UBM sputtering films on Al and SiN under films were 2.2 times differences, indicating 0.475 kN/m for Al/Si wafer and 0.093 kN/m for SiN/Si wafer, respectively.

• Journal of Welding and Joining
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• v.18 no.6
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• pp.74-82
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• 2000

The fluxless wetting properties of UBM-coated Si-wafer to the binary lead-free solders(Sn-Ag, Sn-Sb, Sjn-In, Sn0Bi) were estimated by wetting balance method. With the new wettability indices from the wetting curves of one side coated specimen, the wetting property estimation of UBM-coated Si-wafer was possible. For UBM of Si-chip, Au/Cu/Cr UBm was better than au/Ni/TI in the point of wetting time/ At general reflow process temperature, the wettability of high melting point solders(Sn-Sb, Sn-Ag) was better than that of low melting point one(Sn-Bi, Sn-In). The contact angle of the one side coated Si-plate to the solder could be calculated from the force balance equation by measuring the static state force and the tilt angle.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.1
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• pp.13-16
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• 2000

Progress in Si crystal and wafer technologies is discussed on single crystal growth, wafer fabrication, epitaxial growth, gettering, 300 mm and SOI. As for bulk crystal growth, the mechanism of grown-in defects (voids) formation, the succes of grown-in defect free crystal growth technology and nitrogen doped crystal are shown. New wafer fabrication technologies such as both-side mirror polishing and etchingless process have been developed. The epitaxial growth of SiGe/Si heterostructure for high speed bipolar device is treated. Gettering technology under low temperature process such as RTP is important, and also it is shown that IG effect for Ni could be predicted using computer simulation of precipitate density and size. The development of 300 mm wafer and SOI has made progress steadily.

• Korean Journal of Materials Research
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• v.23 no.1
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• pp.35-40
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• 2013

In this study, the influence on the surface passivation properties of crystalline silicon according to silicon wafer thickness, and the correlation with a-Si:H/c-Si heterojunction solar cell performances were investigated. The wafers passivated by p(n)-doped a-Si:H layers show poor passivation properties because of the doping elements, such as boron(B) and phosphorous(P), which result in a low minority carrier lifetime (MCLT). A decrease in open circuit voltage ($V_{oc}$) was observed when the wafer thickness was thinned from $170{\mu}m$ to $50{\mu}m$. On the other hand, wafers incorporating intrinsic (i) a-Si:H as a passivation layer showed high quality passivation of a-Si:H/c-Si. The implied $V_{oc}$ of the ITO/p a-Si:H/i a-Si:H/n c-Si wafer/i a-Si:H/n a-Si:H/ITO stacked layers was 0.715 V for $50{\mu}m$ c-Si substrate, and 0.704 V for $170{\mu}m$ c-Si. The $V_{oc}$ in the heterojunction solar cells increased with decreases in the substrate thickness. The high quality passivation property on the c-Si led to an increasing of $V_{oc}$ in the thinner wafer. Short circuit current decreased as the substrate became thinner because of the low optical absorption for long wavelength light. In this paper, we show that high quality passivation of c-Si plays a role in heterojunction solar cells and is important in the development of thinner wafer technology.

• Journal of Mechanical Science and Technology
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• v.20 no.6
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• pp.738-747
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• 2006

The friction behaviour of Si-wafer, diamond-like carbon (DLC) and two self-assembled monolayers (SAMs) namely dimethyldichlorosilane (DMDC) and diphenyl-dichlorosilane (DPDC) coated on Si-wafer was studied under loading conditions in milli-newton (mN) range. Experiments were performed using a ball-on-flat type reciprocating micro-tribo tester. Glass balls with various radii 0.25 mm, 0.5 mm and 1 mm were used. The applied normal load was in the range of 1.5 mN to 4.8 mN. Results showed that the friction increased with the applied normal load in the case of all the test materials. It was also observed that friction was affected by the ball size. Friction increased with the increase in the ball size in the case of Si-wafer. The SAMs also showed a similar trend, but had lower values of friction than those of Si-wafer In-terestingly, for DLC it was observed that friction decreased with the increase in the ball size. This distinct difference in the behavior of friction in DLC was attributed to the difference in the operating mechanism. It was observed that Si-wafer and DLC exhibited wear, whereas wear was absent in the SAMs. Observations showed that solid-solid adhesion was dominant in Si-wafer, while plowing in DLC. The wear in these two materials significantly Influenced their friction. In the case of SAMs their friction behaviour was largely influenced by the nature of their molecular chains.

• KSTLE International Journal
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• v.5 no.2
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• pp.37-43
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• 2004

Abstract : Nano/micro-scale friction properties were investigated on Si (100) and three self-assembled monolayers (SAMs) (PFOTC, DMDM, DPDM) coated on Si-wafer by chemical vapor deposition technique. Experiments were conducted at ambient temperature(24$pm$1$circ$C) and humidity(45$pm$5%). Friction at nano-scale was measured using Atomic Force Microscopy (AFM) in the range of 0-40nN normal loads. In both Si-wafer and SAMs, friction increased linearly as a function of applied normal load. Results showed that friction was affected by the inherent adhesion in Ssi-wafer, and in the case of SAMs the physical/chemical structures had a major influence. Coefficient of friction of these test samples at the micro-scale was also energies. In order to study the effect of contact area on coefficient of friction at the micro-scale, friction was measured for Si-wafer and DPDM against Soda Lime balls (Duke Scientiffic Corporation) of different radii (0.25 mm, 0.5 mm and 1 mm) at different applied normal loads (1500, 3000 and 4800 mN). Results showed that Si-wafer had higher coefficient of friction than DPDM. Further, unlike that in the case of DPDM, friction in Si-wafer was severely influenced by its wear. SEM evidences showed that solid-solid adhesion was the wear mechanism in Si-wafer.

• Transactions of the Society of Information Storage Systems
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• v.2 no.2
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• pp.96-99
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• 2006

In this research, a wafer-level transfer method of cantilever away on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.