• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.65-74
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• 2013

The through-silicon via (TSV) technology is essential for 3-dimensional integrated packaging. TSV technology, however, is still facing several reliability issues including interfacial delamination, crack generation and Cu protrusion. These reliability issues are attributed to themo-mechanical stress mainly caused by a large CTE mismatch between Cu via and surrounding Si. In this study, the thermo-mechanical reliability of copper TSV technology is investigated using numerical analysis. Finite element analysis (FEA) was conducted to analyze three dimensional distribution of the thermal stress and strain near the TSV and the silicon wafer. Several parametric studies were conducted, including the effect of via diameter, via-to-via spacing, and via density on TSV stress. In addition, effects of annealing temperature and via size on Cu protrusion were analyzed. To improve the reliability of the Cu TSV, small diameter via and less via density with proper via-to-via spacing were desirable. To reduce Cu protrusion, smaller via and lower fabrication temperature were recommended. These simulation results will help to understand the thermo-mechanical reliability issues, and provide the design guideline of TSV structure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.418-418
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• 2008

The electrochemical etching of silicon in HF-based solutions is known to form various types of porous structures. Porous structures are generally classified into three categories according to pore sizes: micropore (below 2 nm in size), mesopore (2 ~ 50 nm), and macropore (above 50 nm). Recently, the formation of macropores has attracted increasing interest because of their promising characteristics for an wide scope of applications such as microelectromechanical systems (MEMS), chemical sensors, biotechnology, photonic crystals, and photovoltaic application. One of the promising applications of macropores is in the field of MEMS. Anisotropic etching is essential step for fabrication of MEMS. Conventional wet etching has advantages such as low processing cost and high throughput, but it is unsuitable to fabricate high-aspect-ratio structures with vertical sidewalls due to its inherent etching characteristics along certain crystal orientations. Reactive ion dry etching is another technique of anisotropic etching. This has excellent ability to fabricate high-aspect-ratio structures with vertical sidewalls and high accuracy. However, its high processing cost is one of the bottlenecks for widely successful commercialization of MEMS. In contrast, by using electrochemical etching method together with pre-patterning by lithographic step, regular macropore arrays with very high-aspect-ratio up to 250 can be obtained. The formed macropores have very smooth surface and side, unlike deep reactive ion etching where surfaces are damaged and wavy. Especially, to make vertical microwire or nanowire arrays (aspect ratio = over 1:100) on silicon wafer with top-down photolithography, it is very difficult to fabricate them with conventional dry etching. The electrochemical etching is the most proper candidate to do it. The pillar structures are demonstrated for n-type silicon and the formation mechanism is well explained, while such a experimental results are few for p-type silicon. In this report, In order to understand the roles played by the kinds of etching solution and mask patterns in the formation of microwire arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, dimethyl sulfoxide (DMSO), iso-propanol, and mixtures of HF with water on the structure formation on monocrystalline p-type silicon with a resistivity with 10 ~ 20 $\Omega{\cdot}cm$. The different morphological results are presented according to mask patterns and etching solutions.

• Journal of Sensor Science and Technology
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• v.1 no.1
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• pp.23-34
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• 1992

In order to fabricate magnetoresistive sensor, Fe-Ni and Co-Ni alleys were evaporated on the slide glass and the silicon wafers. Saturation magnetic induction($B_{s}$), coercive field strength($H_{c}$) and magnetoresistance were measured for fabricated samples. The evaporated Fe-Ni thin films show that the saturation magnetic induction was 0.65 T, and coercive field strength was 0.379 A/cm, and this value was changed to 0.370 A/cm(//), 0.390 A/cm(${\bot}$), respectively after magnetic annealing. For the measurement of coercive field strength, magnetizing frequency of 1 kHz was used. For the fabricated sensor element, the change of magnetoresistance (${\Delta}R/R$) was excessively unstable due to oxidation in the process of fabrication. The evaporated Co-Ni alloy thin films show that saturation magnetic induction was 0.66 T, and coercive field strengthes were 5.895 A/cm(//), 5.898 A/cm(${\bot}$), respectively, after magnetic annelaing. The change of magnetoresistance(${\Delta}R/R$) was $3.6{\sim}3.7%$ of which value was excessively stable to room temperature. Fe-Ni thin film could have many problems due to large affinity in the process of fabrication of magnetoresistance sensor, but Co-Ni thin film could be a suitable material for fabrication of magnetoresistance sensor, because of its small affinity and definite magnetoresistance effects.

• Proceedings of the Korean Vacuum Society Conference
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• 1998.02a
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• pp.179-179
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• 1998

실리콘 집적회로 제조시 sub-micron 의 contact 형성 공정은 질연막 형성 후 이의 식각 및 세정, c contact 실리사이드, 획산방지막, 배선 금속층의 형성 과정올 거치게 된다. 본 연구팀에서는 C.F야f2 헬리 콘 플라즈마훌 이용한 고선택비 contact 산화막 식각공정시 형성된 잔류막충과 오염 손상올 관찰하고 산소 플라즈마 처리와 후속 열처리에 따른 이들의 제거 정도를 관찰하여 이에 대한 결과를 발표하였다. 본 연구메서는 식각 및 후처리에 따라 잔류하는 잔류막과 손상층이 후속 공정인 contact 실리사이드 형 섬에 미치는 영향올 관찰하였다. C C.F바f2 웰리콘 풀라즈마률 이용한 식각시 공정 변수로는 수소가스 첨가, bias voltage 와 과식각 시간 의 효과를 관찰하였으며 다른 조건은 일정하게 하였다 .. Contact 실리사이드로는 Ti, Co-싫리사이드를 선 택하였으며 Piranha cleaning, 산소 플라즈마 처리, 산소 풀라즈마+600 'C annealing으로 각각 후처리된 시 편을 후처리하지 않은 시펀돌과 함께 실리사이드 형성용‘시펀으로 이용하였다 각각 일정 조건에서 동 일 두께의 실리사이드훌 형성시킨 후 4-point probe룰 이용하여 면저황올 측정하였다 후처리하지 않은 시편의 경무 실리사이드 형성은 아주 시펀의 일부분에서만 형성되었으며 후속 세정 및 얼처리훌 황에 따라 실리사이드의 면저항은 감소하여 식각 과정을 거치지 않은 깨끗한 실리콘 웨이퍼위에 실리사이드 를 형성시킨 값(control 값)에 접근하였다. 실리사이드의 면저항값은 식각시 노훌된 실리콘 표면 위에 형 성된 손상충보다는 잔류막에 큰 영향을 받았으며 수소 가스가 첨가된 식각 가스로 식각한 시편으로 형 성한 실리사이드의 면저항값이 손상이 상대적으로 적은 것으로 관찰된 수소훌 첨가하지 않은 식각 가 스로 식각한 시펀 위에 형성된 실리사이드의 면저황에 비해 낮은 값을 나타내었다. 실리사이드의 전기적 륙성에 미치는 손상층의 영향올 좀더 면밀히 관찰하고자 bare 실리콘 wafer 에 잔류막이 거의 없이 손상층을 유발시키는 식각 조건들 (100% HBr, 100%H2, 100%Ar, Cl싸fz)에 대하여 실 리콘 식각을 수행한 후 Co-실리사이드률 형성하여 이의 면저황을 측정한 걸과 100% Ar 가스로 식각된 시편을 이용하여 형성한 실리사이드의 면저항은 control 에 기까운 면저항값올 지니고 따라서 손상층이 실리사이드 형섬메 미치는 영향은 크지 않음을 알 수 있었다. 이상의 연구 결과훌 통해 손상층이 실리사이드의 형성이나 전기적 톡섬에 미치는 영황은 잔류막층 에 의한 영향보다 적다는 것을 알 수 았으며 잔류막층의 두께보다는 성분이나 걸합상태, 특히 식각 및 후처리 후 잔류하는 탄소 싱분과 C-Si 결함에 큰 영향올 받는 것올 알 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of Sensor Science and Technology
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• v.9 no.1
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• pp.70-75
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• 2000

The recycled single crystal silicon wafers have been fabricated into solar cells. It can be a solution for the high cost in materials for solar cells and recycling of materials. So, p-type (100) single crystal silicon wafers with high resistivity of $10-14\;{\Omega}cm$ and the thickness of $650\;{\mu}m$ were used for the fabrication of solar cells. Optimistic conditions of formation of back surface field, surface texturing and anti-reflection coating were studied for getting high efficiency. In addition, thickness variation of solar cell was also studied for increase of efficiency. As a result, the solar cell with efficiency of 10% with a curve fill factor of 0.53 was fabricated with the wafers which have the area of $4\;cm^2$ and thickness of $300\;{\mu}m$. According to above results, recycling possibility of wasted wafers to single crystal silicon solar cells was confirmed.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.330-332
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• 2013

소 분위기에서 플라즈마 표면 처리의 경우 기판 표면에 존재하는 수소와 탄소 유기물들이 산소와 반응하여 $H_2O$와 $CO_2$ 등으로 제거되며 표면에 오존 결합을 유도하여 표면 에너지를 증가시키는 것으로 알려져 있다. ZnO 나노구조물을 성장시키는 방법으로는 MOCVD (Metal-Organic Chemical Vapor Deposited), PLD (Pulsed Laser Deposition), VLS (Vapor-Liquid-Solid), Sputtering, 습식화학합성법(Wet Chemical Method) 방법 등이 있다. 그중에서도 습식화학합성법은 쉽게 구성요소를 제어할 수 있고, 저비용 공정과 낮은 온도에서 성장 가능하며 플렉서블 소자에도 적용이 가능하다. 그러므로 본 연구에서는 플라즈마 표면처리에 따라 표면에너지를 변화하여 습식화학합성법으로 성장시킨 ZnO nanorods의 밀도를 제어하고 photolithography 공정 없이 패터닝 가능성을 유 무를 판단하는 연구를 진행하였다. 기판은 Si wafer (100)를 사용하였으며 세척 후 표면에너지 증가를 위한 플라즈마 표면처리를 실시하였다. 분위기 가스는 Ar/$O_2$를 사용하였으며 입력전압 400 W에서 0, 5, 10, 15, 60초 동안 각각 실시하였다. ZnO nanorods의 seed layer를 도포하기 위하여 Zinc acetate dehydrate [Zn $(CH_3COO)_2{\cdot}2H_2O$, 0.03 M]를 ethanol 50 ml에 용해시킨 후 스핀코팅기를 이용하여 850 RPM, 15초로 5회 실시하였으며 $80^{\circ}C$에서 5분간 건조하였다. ZnO rods의 성장은 Zinc nitrate hexahydrate [$Zn(NO_3)_2{\cdot}6H_2O$, 0.025M], HMT [$C6H_{12}N_4$, 0.025M]를 deionized water 250 ml에 용해시켜 hotplate에 올리고 $300^{\circ}C$에서 녹인 후 $200^{\circ}C$에서 3시간 성장시켰다. ZnO nanorods의 성장 공정은(Fig. 1)과 같다. 먼저 플라즈마 처리한 시편의 표면에너지 측정을 위해 접촉각 측정 장치[KRUSS, DSA100]를 이용하였다. 그 결과 0, 5, 10, 15, 60 초로 플라즈마 표면 처리했던 시편이 각각 Fig. l, 2와 같이 $79^{\circ}$, $43^{\circ}$, $11^{\circ}$, $6^{\circ}$, $7.8^{\circ}$로 측정되었으며 이것을 각각 습식화학합성법으로 ZnO nanorods를 성장 시켰을 때 Fig. 3과 같이 밀도 차이를 확인할 수 있었다. 이러한 결과를 바탕으로 기판의 표면에너지를 제어하여 Fig. 4와 같이 나타나며 photolithography 공정없이 ZnO nanorods를 패터닝을 할 수 있었다. 본 연구에서는 플라즈마 표면 처리를 통하여 표면에너지의 변화를 제어함으로써 ZnO nanorods 성장의 밀도 차이를 나타냈었다. 이러한 저비용, 저온 공정으로 $O_2$, CO, $H_2$, $H_2O$와 같은 다양한 화학종에 반응하는 ZnO를 이용한 플렉시블 화학센서에 응용 및 사용될 수 있고, 플렉시블 디스플레이 및 3D 디스플레이 소자에 활용 가능하다.

• Journal of Adhesion and Interface
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• v.22 no.2
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• pp.57-62
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• 2021

Recently, the atomically thin two-dimensional transition-metal dichalcogenides (TMDs) have received considerable attention for the application to next-generation semiconducting devices, owing to their remarkable properties including high carrier mobility. However, while a technique for growing graphene is well matured enough to achieve a wafer-scale single crystalline monolayer film, the large-area growth of high quality TMD monolayer is still a challenging issue for industrial application. In order to enlarge the size of single crystalline MoS₂ monolayer, here, we systematically investigated the effect of process parameters in molten-salt-assisted chemical vapor deposition method. As a result, with optimized process parameters, we found that single crystalline monolayer MoS₂ can be grown as large as 420 ㎛.