• 반도체디스플레이기술학회지
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• 제18권4호
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• pp.12-17
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• 2019

In this study, the Ag nano-dots structure and silicon nitride film were applied to the textured wafer surface to improve the light trapping effect of mono-crystalline silicon solar cell. Ag nano-dots structure was formed by performing a heat treatment for 30 minutes at 650℃ after the deposition of 10nm Ag thin film. Ag thin film deposition was performed using a thermal evaporator. The silicon nitride film was deposited by a Hot-wire chemical vapor deposition. The effect of light trapping was compared and analyzed through light reflectance measurements. Experimental results showed that the reflectivity increased by 0.5 ~ 1% under all nitride thickness conditions when Ag nano-dots structure was formed before nitride film deposition. In addition, when the Ag nano-dots structure is formed after deposition of the silicon nitride film, the reflectance is increased in the nitride film condition of 70 nm or more. When the HF treatment was performed for 60 seconds to improve the Ag nano-dot structure, the overall reflectance was improved, and the reflectance was 0.15% lower than that of the silicon nitride film-only sample at 90 nm silicon nitride film condition.

• 센서학회지
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• 제9권1호
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• pp.70-75
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• 2000

단결정 실리콘웨이퍼를 사용한 태양전지 제조에 있어 가장 큰 문제점은 재료의 높은 가격이다. 본 연구에서는 이러한 문제의 해결방안으로 현재 DRAM 소자 제조과정에서 폐기되는 웨이퍼를 리사이클링하여 태양전지를 제작하고 저가의 제조공정과 전지의 특성을 연구하였다. DRAM용 실리콘 웨이퍼는 비저항이 높고 두꺼워 태양전지 재료로서 부적합하나, 본 연구에서는 후면전계 (Back Surface Field) 형성, 표면 Texturing, 반사 방지막 형성 등의 공정들을 조합하여 효율향상을 위한 최적조건을 찾아내고, 두께변화에 따른 효율변화를 조사하였다. 최적화된 위의 모든 조건들을 적용하였을 때, $4\;cm^2$의 면적, $300\;{\mu}m$ 두께를 가지는 태양전지에서 단락전류밀도 ($J_{sc}$)는 $28\;mA/cm^2$, 개방전압 ($V_{oc}$) 0.51V, 충실도(Fill Factor)면에서는 0.53으로 가장 높은 값을 얻었고, 10% 이상의 효율을 확보할 수 있었다. 이와 같은 방법으로 폐기되는 실리콘 웨이퍼들을 재활용하여 실용성이 큰 저가의 단결정 실리콘 태양전지를 제작할 수 있는 방법을 확보할 수 있었다.

• 센서학회지
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• 제23권3호
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• pp.185-191
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• 2014

The width of depletion region in a varactor diode can be modulated by varying a reverse bias voltage. Thus, the preferred characteristics of depletion capacitance can obtained by the change in the width of depletion region so that it can select only the desirable frequencies. In this paper, the TV tuner varactor diode fabricated by hyper-abrupt profile control technique is presented. This diode can be operated within 3.3 V of driving voltage with capability of UHF band tuning. To form the hyperabrupt profile, firstly, p+ high concentration shallow junction with $0.2{\mu}m$ of junction depth and $1E+20ions/cm^3$ of surface concentration was formed using $BF_2$ implantation source. Simulation results optimized important factors such as epitaxial thickness and dose quality, diffusion time of n+ layer. To form steep hyper-abrupt profile, Formed n+ profile implanted the $PH_3$ source at Si(100) n-type epitaxial layer that has resistivity of $1.4{\Omega}cm$ and thickness of $2.4{\mu}m$ using p+ high concentration Shallow junction. Aluminum containing to 1% of Si was used as a electrode metal. Area of electrode was $30,200{\mu}m^2$. The C-V and Q-V electric characteristics were investigated by using impedance Analyzer (HP4291B). By controlling of concentration profile by n+ dosage at p+ high concentration shallow junction, the device with maximum $L_F$ at -1.5 V and 21.5~3.47 pF at 0.3~3.3 V was fabricated. We got the appropriate device in driving voltage 3.3 V having hyper-abrupt junction that profile order (m factor) is about -3/2. The deviation of capacitance by hyper-abrupt junction with C0.3 V of initial capacitance is due to the deviation of thermal process, ion implantation and diffusion. The deviation of initial capacitance at 0.3 V can be reduced by control of thermal process tolerance using RTP on wafer.

• 한국재료학회지
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• 제5권1호
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• pp.42-54
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• 1995

$Ta_2O_5$박막은 고유전율의 특성으로 차세대 DRAM캐패시터 물질로 유망받고 있는 물질이다. 본 연구에서는 p-type(100)Si 웨이퍼 위에 열 MOCVD 방법으로 $Ta_2O_5$박막을 성장시켰으며 기판온도, 버블러 온도, 반응압력의 조업조건이 미치는 영향을 고찰하엿다. 증착된 박막은 SEM, XRD, XPS, FT-IR, AES, TEM, AFM을 이용하여 분석하였으며 질소나 산소 분위기의 furnace 열처리 (FA)와 RTA(Rapid Thermal Annealing)를 통하여 열처리 효과를 살펴보았다. 반응온도에 따른 증착속도는 300 ~ $400 ^{\circ}C$ 범위에서 18.46kcal/mol의 활성화 에너지를 가지는 표면반응 율속단계와 400 ~ $450^{\circ}C$ 범위에서 1.9kcal/mol의 활성화 에너지를 가지는 물질전단 율속단계로 구분되었다. 버블러 온도는 $140^{\circ}C$일때 최대의 증착속도를 보였다. 반응압력에 따른 증착속도는 3torr에서 최대의 증착속도를 보였으나 굴절율은 0.1-1torr사이에 $Ta_2O_5$의 bulk값과 비슷한 2.1정도의 양호한 값이 얻어졌다. $400^{\circ}C$에서 층덮힘은 85.71%로 매우 양호하게 나타났으며 몬테카를로법에 의한 전산모사 결과와의 비교에 의해서 부착계수는 0.06으로 나타났다. FT-IR, AES, TEM 분석결과에 의하여 Si와 $Ta_2O_5$ 박막 계면의 산화막 두께는 FA-$O_{2}$ > RTA-$O_{2}$ ~ FA-$N_{2}$ > RTA-$N_{2}$ 순으로 성장하였다. 하지만 질소분위기에서 열처리한 박막은 산소분위기의 열처리경우에 비해 박막내의 산소성분의 부족으로 인한 그레인 사이의 결함이 많이 관찰되었다.

• 공업화학
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• 제10권5호
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• pp.644-651
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• 1999

본 연구에서는 진공 증착법을 이용하여 철프탈로시아닌(FePc) 박막을 실리콘 웨이퍼와 알루미나 기판 위에 합성하였으며, 박막의 증착 온도와 두께를 변화시켜 실험한 후 일부의 박막을 열처리하였다. 박막의 두께 변화에 따른 표면 구조 변화, 상전이와 전기 저항 감도 변화를 SEM, XRD, 그리고 전기저항의 측정으로 관찰하였다. 증착 온도가 $370^{\circ}C$에서 $350^{\circ}C$로 감소함에 따라 $\alpha$상의 (200)면, (011)면, (211)면, 그리고 (114)면이 사라지며 $\beta$상의 (100)면의 피크가 나타났다. 전구물질의 양을 달리하며 고속 증착시켜 박막 두께를 조절한 결과, 두께 증가에 따라 결정 크기가 증가하고 또한 $\alpha$상에서 $\beta$상으로의 상 전이가 일어남을 알 수 있었다. 열처리한 박막의 결정성을 측정한 결과 열처리 온도가 증가함에 따라 $150^{\circ}C$으로부터 $\alpha$상에서 $\beta$상으로의 상 전이가 일어나기 시작하여 $350^{\circ}C$에서 완전히 $\beta$상으로 전이되었다. $NO_x$에 대한 철프탈로시아닌 박막의 온도에 따른 전기저항감도를 측정한 결과 박막의 두께가 얇을수록 더 좋고 안정된 전기 저항 감도를 보여주었다. 즉 박막의 표면구조가 조밀하게 성장할수록 전기 저항 감도가 더욱 좋아짐을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.137-137
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• 2009

Thin-film transistors (TFTs) that can be prepared at low temperatures have attracted much attention due to the great potential for flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited by low field effect mobility or rapidly degraded after exposing to air in many cases. Another approach is amorphous oxide semiconductors. Amorphous oxide semiconductors (AOSs) have exactly attracted considerable attention because AOSs were fabricated at room temperature and used lots of application such as flexible display, electronic paper, large solar cells. Among the various AOSs, a-IGZO was considerable material because it has high mobility and uniform surface and good transparent. The high mobility is attributed to the result of the overlap of spherical s-orbital of the heavy pest-transition metal cations. This study is demonstrated the effect of thickness channel layer from 30nm to 200nm. when the thickness was increased, turn on voltage and subthreshold swing were decreased. a-IGZO TFTs have used a shadow mask to deposit channel and source/drain(S/D). a-IGZO were deposited on SiO2 wafer by rf magnetron sputtering. using power is 150W, working pressure is 3m Torr, and an O2/Ar(2/28 SCCM) atmosphere at room temperature. The electrodes were formed with Electron-beam evaporated Ti(30nm) and Au(70nm) structure. Finally, Al(150nm) as a gate metal was evaporated. TFT devices were heat treated in a furnace at $250^{\circ}C$ in nitrogen atmosphere for an hour. The electrical properties of the TFTs were measured using a probe-station to measure I-V characteristic. TFT whose thickness was 150nm exhibits a good subthreshold swing(S) of 0.72 V/decade and high on-off ratio of 1E+08. Field effect mobility, saturation effect mobility, and threshold voltage were evaluated 7.2, 5.8, 8V respectively.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.418-418
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• 2008

The electrochemical etching of silicon in HF-based solutions is known to form various types of porous structures. Porous structures are generally classified into three categories according to pore sizes: micropore (below 2 nm in size), mesopore (2 ~ 50 nm), and macropore (above 50 nm). Recently, the formation of macropores has attracted increasing interest because of their promising characteristics for an wide scope of applications such as microelectromechanical systems (MEMS), chemical sensors, biotechnology, photonic crystals, and photovoltaic application. One of the promising applications of macropores is in the field of MEMS. Anisotropic etching is essential step for fabrication of MEMS. Conventional wet etching has advantages such as low processing cost and high throughput, but it is unsuitable to fabricate high-aspect-ratio structures with vertical sidewalls due to its inherent etching characteristics along certain crystal orientations. Reactive ion dry etching is another technique of anisotropic etching. This has excellent ability to fabricate high-aspect-ratio structures with vertical sidewalls and high accuracy. However, its high processing cost is one of the bottlenecks for widely successful commercialization of MEMS. In contrast, by using electrochemical etching method together with pre-patterning by lithographic step, regular macropore arrays with very high-aspect-ratio up to 250 can be obtained. The formed macropores have very smooth surface and side, unlike deep reactive ion etching where surfaces are damaged and wavy. Especially, to make vertical microwire or nanowire arrays (aspect ratio = over 1:100) on silicon wafer with top-down photolithography, it is very difficult to fabricate them with conventional dry etching. The electrochemical etching is the most proper candidate to do it. The pillar structures are demonstrated for n-type silicon and the formation mechanism is well explained, while such a experimental results are few for p-type silicon. In this report, In order to understand the roles played by the kinds of etching solution and mask patterns in the formation of microwire arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, dimethyl sulfoxide (DMSO), iso-propanol, and mixtures of HF with water on the structure formation on monocrystalline p-type silicon with a resistivity with 10 ~ 20 $\Omega{\cdot}cm$. The different morphological results are presented according to mask patterns and etching solutions.