• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.6
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• pp.1113-1120
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• 2022

In this paper, a communication methodology for the digital FRTU(: Feeder Remote Terminal Unit) required by the smart grid distribution system was studied. The digital FRTU consists of a fault handling unit and a communication unit. The fault handling unit transmits fault information to the communication unit in case of a failure, and the communication unit is designed to autonomously determine the fault section through two-way communication between surrounding digital FRTUs. For performance verification, a performance verification system consisting of 3 line sections based on 3 digital FRTUs was constructed to enable fault simulation for various failure scenarios. Various fault cases including one phase ground fault, line-to-line short-circuit fault, and three-phase short-circuit fault were experimentally simulated on the established performance verification system, and the validity of the developed methodology was confirmed by proving the accurate fault section inference results for each fault simulation case.

• Journal of Korea Society of Industrial Information Systems
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• v.24 no.2
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• pp.41-46
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• 2019

The application of series compensator in a power system affects other devices such as circuit breakers transient recovery voltage (TRV) problem. In this paper, we analyze the TRV effect on a line circuit breaker in the cases with and without thyristor-controlled series capacitor (TCSC) via simulation, and suggest an effective method to overcome the increase of TRV due to the TCSC installation. It also discusses the impact of proposed protection on metal oxide varistor (MOV). A 345 kV transmission line in Korea was selected as a study case. Grid system was modelled using PSCAD (Power Systems Computer Aided Design) / EMTDC(Electro Magnetic Transient Direct Current). The TRV was analyzed by implementing a short circuit fault along the transmission line and at the breaker terminal. The proposed protection scheme, the TRV satisfies the standard. However, the MOV energy capacity increased as the delay time increased. This result can solve the TRV problem caused by the expected transmission line fault in a practical power system.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.05b
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• pp.175-179
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• 2005

The main objective of this paper is to module design and pressure relief test a new type of polymer gapless surge arrester for power distribution line. Metal oxide surge arrester for most electric power system applications, power distribution line and electric train are now being used extensively to protect overvoltage due to lightning. Surge arresters with porcelain housing must not have explosive breakage of the housing to minimize damage to other equipment when subjected to internal high short circuit current. When breakdown of gapless elements in a surge arrester occurs due to flashover, fault short current flows through the arrester and internal pressure of the arrester rises. The pressure rise can usually be limited by fitting a pressure relief diaphragm and transferring the arc from the inside to the outside of the housing. However, there is possibility of porcelain fragmentation caused by the thermal shock, pressure rise, etc. Non-fragmenting of the housing is the most desired way to prevent damage to other equipment. The pressure change which is occurred by flashover become discharge energy. This discharge energy raises to damage arrester housing and arrester housing is dispersed as small fragment. Therefore, the pressure relief design is requested to obstruct housing dispersion.

• Journal of Advanced Marine Engineering and Technology
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• v.32 no.6
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• pp.964-973
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• 2008

In this study, a short-wavelength coplanar-type transmission line employing periodic ground structure (PGS) was developed for application to miniaturized on-chip passive component on Si Radio Frequency Integrated Circuit (RFIC). The transmission line employing PGS showed shorter wavelength and lower characteristic impedance than conventional coplanar-type transmission line. The wavelength of the transmission line employing PGS structure was 57 % of the conventional coplanar-type transmission line on Si substrate. Using the theoretical analysis. basic characteristics of the transmission line employing PGS (e.g., bandwidth. loss, impedance, and resonance characteristics) were also investigated in order to evaluate its suitability for application to a development of miniaturized passive on-chip components on silicon RFIC. According to the results. the bandwidth of the transmission line employing PGS was more than 895 GHz as long as T is less than 20${\mu}m$, and the resonance characteristic was observed in 1239 GHz, which indicates that the PPGM structure is a promising candidate for application to a development of miniaturized on-chip passive components on Si RFIC.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.4
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• pp.243-250
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• 2005

Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.535-538
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• 1994

In this paper, an isolated ZVS-PWM boost converter is proposed for single stage line conversion. For power factor correction, we used the half bridge topology at the primary side of isolation transformer permitting switching devices to operate under ZVS by using circuit parastics and operating at a fixed duty ratio near 50%. Thus the relatively continuous input current distortion and small size input filter are also achievable. The ZVS-PWM boost operation of the proposed converter can be achieved by using the boost inductor $L_f$, main switch $Q_3$, and simple auxiliary circuit at the secondary side of isolation transformer. The secondary side circuit differ from a conventional PWM boost converter by introduction a simple auxiliary circuit. The auxiliary circuit is actived only during a short switching transition time to create the ZVS condition for the main switch as that of the ZVT-PWM boost converter. With a single stage, it is possible to achieve a sinusoidal line current at unity power factor as well as the isolated 48V DC output. Comparing to the two stage schemes, overall effiency of the proposed converter is highly improved due to the effective ZVS of all devices as well as single stage power conversion. Thus, it can be operated at high switching frequency allowing use of small size input filter. Minimum voltage and current stress make it high power application possible.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.53 no.7
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• pp.397-404
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• 2004

This paper describes a study of transient characteristics in 765kV untransposed transmission lines. As the 765(kV) system can carry bulk power, some severe fault on the system nay cause large system disturbance. The large shunt capacitance and small resistance of 765kv transmission line make various difficulties for its protection. These problems including current difference between sending and receiving terminals on normal power flow, low order harmonic current component in fault current and current transformer saturation due to the long DC time constant of the circuit etc. must be investigated and solved. The analysis of transient characteristics at sending terminal has been carried out for the single phase to ground fault and 3-phase short fault, etc. The load current, charging current in normal condition and line flows, fault current, THD(Total Harmonic Distortion) of harmonics, time constants have been analysed for the 765kV untransposed transmission line systems.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1811-1813
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• 2001

In order to obtain the useful data for quality control of the pole transformer and supply the stable electric power in distribution line, The evaluation of performance for low-loss pole transformer had been performed for new products and ones under operation for several years in distribution line. As the results, we found that the rate of fail were very high in gaskette, short-circuit strength and temperature-rise test, especially 48 percent in gaskette test.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.02a
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• pp.261-262
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• 2003

We performed unsymmetrical analysis of a single line-to-ground fault in a three-phase system. The current limiting elements were meander type YBCO stripes coated with Au shunt. When the fault occurred, short circuit currents were effectively limited within 1-2 msec after fault instant. The unsymmetrical rate of fault phase was distributed from 6.4 to 1.4 and most of the fault current flowed in the grounding line due to its direct grounding system.

• Proceedings of the KIEE Conference
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• 2003.11a
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• pp.154-157
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• 2003

The exicting short circuit analysis calculate the current with the balance system and unbalance fault impedance. That method deal with only bus fault with the consequence that line fault study is irrational. This paper propose the line fault, shunt unbalance and series unbalance analysis method using template concept that is one of advantages for OOP(Object-Oriented Programming). This method is possible to use for calculating inductive distrubance.