• Journal of Welding and Joining
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• v.21 no.1
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• pp.48-53
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• 2003

The object of this study is to examine the effect of short circuit time ratio (SCTR) and current rise delay time (Td) on the spatter generation at low and medium current range in $CO_2$ welding. The spatter was evaluated by the weight generated in the welding of bead-on-plate for 30 seconds (3 times). Td was varied by order of 0, 0.4, 0.8 and 1.2 msec. At each Td, the short circuit time ratio was varied by the output voltage of the welding power source. In the low current range, it was found that the optimum SCTR was 20~25%, and the minimum spatter generation weight was obtained in the case of Td=0.4msec and SCTR=22% even though the remarkable difference was not showed by the application of Td. In the medium current range, it was confirmed that the arc was stable though the SCTR was increased from 20% to 40% by the control of current wave. Spatter generation weight depended on the variation of Td, and the lowest value of spatter generation weight occurred at Td=0.8~1.2msec.

• Proceedings of the KWS Conference
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• 2001.10a
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• pp.33-36
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• 2001

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.3
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• pp.40-46
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• 2001

In this paper, a novel low power full adder circuit comprising only 10 transistors is proposed. The circuit is based on the six -transistor CMOS XOR circuit, which generates both XOR and XNOR signals and pass transistors. This adder circuit provides a good low power characteristics due to the smaller number of transistors and the elimination of short circuit current paths. Layouts have been carried out using a 0.65 ${\mu}m$ ASIC design rule for evaluation purposes. The physical design has been evaluated using HSPICE at 25MHz to 50MHz. The proposed circuit has been used to build 2bit and 8bit ripple carry adders, which are used for evaluation of power consumption, time delay and rise and fall time. The proposed circuit shows substantially improved power consumption characteristics, about 70% lower than transmission gate full adder (TFA), and 60% lower than a design using 14 transistors (TR14). Delay and signal rise and fall time are also far shorter than other conventional designs such as TFA and TR14.