• Proceedings of the KIEE Conference
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• 2005.11b
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• pp.49-51
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• 2005

The saturation of transformer for short-circuit test suppress the peak current value during the test. And such phenomenon effect on the test results occasionally. This paper deals with the induction of the formula to restore the peak current value from the measured data.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1527-1528
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• 2006

This paper presents short-circuit tests for polymer-housed distribution arrestors depends on standards. The compared standards are IEC 60694(2004) and IEEE C62.11 (2005). Major differences depends on standards are prefaulted(pre-failure) method by means of a fuse wire and test procedure.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.4
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• pp.243-250
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• 2005

Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.6
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• pp.267-272
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• 2002

This Paper deals with the short circuit tests of the three-Phase DC reactor type fault current limiter (FCL) in changing of turns ratio of transformers. The experiment of this paper is a preliminary step to develop the FCL's faculties for an application to high voltage transmission line. So, superconducting coil was made of Nb-Ti, low temperature superconductor, and the ratings of the power system of experimental circuit are 400V/7A class. A three-phase DC reactor type FCL consists of three transformers, six diodes, one superconducting coil and one cryostat. The important point of experimental analysis is transient period, the operating lagging time of circuit breaker. As the results of the experiment, the values are referred to the limitation rate about 77% and 90% when the turns ratio of transformer was 1:1 and 2:1 respectively.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.1
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• pp.93-100
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• 2011

This paper presents a technical study for the first short stroke lightning current generator using a crowbar device. The so-called crowbar-technology is most common to make 10/350[${\mu}s$] impulse currents with high amplitude, and the lightning current generator with crowbar device has an economic advantage than the nominal RLC current generator. But both the operating efficiency and the operating reliability of crowbar spark gap are very important to design the current generator. So, the peaking circuit which consists of small capacitors and a spark gap is applied. And the multi-step coil for controlling the circuit constant at the different test conditions is used. The presented test facility is designed to perform impulse tests with amplitudes up to 50[kA] of 10/350[${\mu}s$].

• Journal of Welding and Joining
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• v.33 no.3
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• pp.47-53
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• 2015

By the trends of electronic package to be more integrative, the fine Cu trace pitch of organic PCB is required to be a robust design. In this study, the short circuit failure mechanism of PCB with a Cl element under the Temperature humidity bias test ($85^{\circ}C$/85%RH/3.5V) was examined by micro-structural study. A focused ion beam (FIB) and an electron probe micro analysis (EPMA) were used to polish the cross sections to reveal details of the microstructure of the failure mode. It is found that $CuCl_x$ were formed and grown on Cu trace during the $170^{\circ}C$/3hrs and that $CuCl_x$ was decomposed into Cu dendrite and $Cl_2$ gas during the $85^{\circ}C$/85%RH/3.5V. It is suggested that Cu dendrites formed on Cu trace lead to a short circuit failure between a pair of Cu traces.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.328-332
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• 2010

The SLF(Short Line Fault) breaking capability test for high voltage class $SF_6$ GCB(Gas Circuit Breaker) was conducted. Simplified LC resonant circuit test facility was used for SLF breaking test. During test, Test current was measured by Rogwski coil and arc voltage was measured by voltage divider. Arc conductance was calculated by using these test results before 200ns at current zero. Critical arc conductance value at rated voltage 145kV class is about 2.3mS regardless of breaking current magnitude and arc conductance value at rated voltage 170kV class is about 2.6mS.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.100-105
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• 2003

In this paper, we propose the novel test method effectively to detect short and open faults in CMOS op-amp. The proposed method uses a sinusoidal signal with higher frequency than unit gain bandwidth. Since the proposed test method doesn't need complex algorithm to generate test pattern, the time of test pattern generation is short, and test cost is reduced because a single test pattern is able to detect all target faults. To verify the proposed method, CMOS two-stage operational amplifier with short and open faults is designed and the simulation results of HSPICE for the circuit have shown that the proposed test method can detect short and open faults in CMOS op-amp.

• Proceedings of the KIEE Conference
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• 1983.07a
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• pp.98-100
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• 1983

• Proceedings of the KIEE Conference
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• 2008.11a
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• pp.150-152
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• 2008

It is necessary to improve the time efficiency in the high power testing station because tests are mainly performed by high-priced equipment. Minimizing a human error through building the database of relevant standards is possible to expect reliable tests. And also, application program that is properly customized for the certain laboratory's power system will help test engineer to easily analyze the phenomenon that is happened in short-circuit and load switching tests. This paper introduces the several functions of the application program that is developed in order to realize these requirements.