• 대한전기학회논문지:전력기술부문A
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• 제48권2호
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• pp.119-126
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• 1999

Current transformer (CT) saturation may cause a variety of protective relays to malfunction. The conventional CT is designed that it can carry up to 20 times the rated current without exceeding 10% ratio error. However, the possibility of CT saturation still remains if the fault current contains substantial amounts of ac and/or dc components. This paper presents a design method of iron-cored CTs for use with protective relays to prevent CT saturation. The proposed design method determines the core cross section of the CT; it employs the transient dimensioning factor to consider relay's operating time (duty cycle) and dc component as well as ac components contained in the fault current, and symmetrical short-circuit current factor to consider as well as ac components contained in the fault current, and symmetrical short-circuit current factor to consider the biggest fault current. The method designs the cross section of CTs in cases of reclosure and no reclosure.

• IEIE Transactions on Smart Processing and Computing
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• 제3권6호
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• pp.425-429
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• 2014

This paper proposes a DC-DC Buck-Converter with DT-CMOS (Dynamic Threshold-voltage MOSFET) Switch. The proposed circuit was evaluated and compared with a CMOS switch by both the circuit and device simulations. The DT-CMOS switch reduced the output ripple and the conduction loss through a low on-resistance. Overall, the proposed circuit showed excellent performance efficiency compared to the converter with conventional CMOS switch. The proposed circuit has switching frequency of 1.2MHz, 3.3V input voltage, 2.5V output voltage, and maximum current of 100mA. In addition, this paper proposes a SCP (Short Circuit Protection) circuit to ensure reliability.

• Journal of international Conference on Electrical Machines and Systems
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• 제3권2호
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• pp.190-199
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• 2014

In the last years, fault problem in power electronics has been more and more investigated both from theoretical and practical point of view. The fault problem can cause equipment failure, data and economical losses. And the analyze system require to ensure fault problem and also rectify failures. The current errors on these faults are applied for identified type of faults. This paper presents technique to detection and identification faults in three-phase voltage source inverter (VSI) by using time-frequency distribution (TFD). TFD capable represent time frequency representation (TFR) in temporal and spectral information. Based on TFR, signal parameters are calculated such as instantaneous average current, instantaneous root mean square current, instantaneous fundamental root mean square current and, instantaneous total current waveform distortion. From on results, the detection of VSI faults could be determined based on characteristic of parameter estimation. And also concluded that the fault detection is capable of identifying the type of inverter fault and can reduce cost maintenance.

• 한국정보전자통신기술학회논문지
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• 제11권5호
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• pp.586-592
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• 2018

본 논문은 140W 급 저면적 LED 전원 제어 회로 설계를 위해 다양한 기능이 집적된 HIC를 제안한다. 제안된 HIC는 정전압/정전류 구동회로, 단락 보호회로, 내부 정전압회로, dimmer 회로를 하나로 집적해, 제작 시 기존 시스템 대비 PCB 가로 길이를 16% 절감하는 효과를 보였다. 다양한 실험을 통해 HIC 내부에 설계된 각 블록의 성능을 검증했고, (정전압 구동회로 변동률 2.9%, dimmer 회로 오차 5%이내, 720 mA에서 안정적인 short protection) 제안된 HIC를 적용해 시스템에서 필요로 하는 전력 대비 PCB 면적을 상당히 줄일 수 있기 때문에, 제작 시간의 대부분을 차지하는 PCB 제조시간을 단출할 수 있는 효과와 전원 제어 회로에서 발생하는 불량에 대해 기존과 같이 PCB 전체를 교체하지 않고 HIC만 교체할 수 있도록 하여 유지/보수를 쉽게 할 수 있는 효과를 기대한다.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 추계학술대회 논문집
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• pp.205-208
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• 2003

Maximum short circuit current of modern power system is becoming so large that the current should transmission capability. Although there are various kinds of method to solve this, approached from super conductivity Fault Current Limiter application viewpoint among them. High Temperature Superconductor-Fault Current Limiter (HTS-FCL) development is progressing according to HTS technology development, and system application is tried. For actual system application of such super conductivity FCL, an efficient method to find FCL locations suitable for reduction of short circuit currents of more than one fault location is developed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 추계학술대회 논문집 전력기술부문
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• pp.321-323
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• 2003

Maximum short circuit current of modern power system is becoming so large that the current should transmission capability. Although there are various kinds of method to solve this, approached from super conductivity Fault Current Limiter application viewpoint among them. High Temperature Superconductor-Fault Current Limiter(HTS-FCL) development is progressing according to HTS technology development, and system application is tried. For actual system application of such super conductivity FCL, an efficient method to find FCL locations suitable for reduction of short circuit currents of more than one fault location is developed.

• 한국초전도ㆍ저온공학회논문지
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• 제5권2호
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• pp.1-7
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• 2003

Nowadays, one of the serious problems in KEPCO(Korea Electric Power Co-Operation) system is the more higher fault current than the SCC(Short Circuit Capacity) of circuit breaker. There are many alternatives to reduce the increased fault current such as isolations of bus ties, enhancement of SCC of circuit breaker, applications of HVDC-BTB(High Voltage Direct Current-Back to Back) and FCL(fault current limiter). But, these alternatives have some drawbacks in viewpoints of system stability and cost. As the superconductivity technology has been developed, the HTS-FCL(High Temperature Superconductor -Fault Current Limiter) can be one of the attractive alternatives to solve the fault current problem. Under this background, this paper presents the EMTDC(Electro-Magnetic Transient Direct Current) model for resistance type HTS-FCL considering the nonlinear characteristic of final resistance value when quenching phenomena occur.

• Journal of Electrical Engineering and Technology
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• 제12권6호
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• pp.2278-2288
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• 2017

Multilevel converter topologies are widely used in many applications. The cascaded H-bridge multilevel inverter (CHBMI), which is one of many multilevel converter topologies, has been introduced as a useful topology in high and medium power. However, it has a drawback to require a lot of switches. Therefore, the reliability of CHBMI is important factor for analyzing the performance. This paper presents a simple switch fault diagnosis method for single-phase CHBMI. There are two types of switch faults: open-fault and short-fault. In the open-fault, the body diode of faulty switch provides a freewheeling current path. However, when the short-fault occurs, the distortion of output current is different from that of the open-fault because it has an unavailable freewheeling current flow path due to a disconnection of fuse. The fault diagnosis method is based on the zero current time analysis according to zero-voltage switching states. Using the proposed method, it is possible to detect the location of faulty switch accurately. The PSIM simulation and experimental results show the effectiveness of proposed switch fault diagnosis method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 A
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• pp.551-553
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• 2002

The cubicle type GIS rated at 25.8kV has been designed and manufactured by Jinkwang E&C eacently with their own technologies and KERI's assistances. The C-GIS has been tested to check the design capability for reference before conducting the type test. The operating characteristics test, short time withstand current and peak withstand current test, basic short circuit test duty T60 for preconditioning test, cable charging current switching test, capacitor bank current switching test, basic short circuit test duty T100s and T100a, single phase earth fault test, double earth fault test has been conducted. The test results show that the design and the manufacturing of the C-GIS has an enough capability to pass through the type test except the occurrence of 2 NSDDs in the cable charging current switching test and the instability of opening time at the minimum operating voltage. The problems shown in the tests will be improved soon and the successful pass will be expected in the following type test.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2009년도 춘계학술대회 논문집
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• pp.80-82
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• 2009

The dependence of the efficiency characteristics of hydrogenated amorphous silicon single junction solar cells on the various intrinsic layer thickness has been investigate in the glass/$SnO_2$:F/p,i,n a-Si:H/Al type of amorphous silicon solar cells by cluster PECVD system. The open circuit voltage, short circuit current, fill factor and conversion efficiency have been measured under AM 1.5 condition. The result of the cell performance was improved about 8.2% due to an increase in the short circuit current.