• Analytical Science and Technology
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• v.6 no.3
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• pp.345-348
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• 1993

A monchromator controller has been built to drive directly by a personal computer. This controller gives better conveniency and accuracy on spectroscopic experiment when a monochromator has deficient driver. This controller consists with simple electronic circuit and control program. The original spectroscopic precision is retained by using stepper motor. The rate changing method is adopted for short slew time. And the scanning is synchronized with spectrum recording device. Because the controller includes electronic counting ciruit, other program can be executed on personal computer during monochromator scanning.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2000.11a
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• pp.99-103
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• 2000

본 논문에서는 FM Reflectometry를 이용하여 마이크로파 대역에서 다양한 전송선로의 분산특성을 측정하였다. 실험에 사용된 전송선로는 도파관에 금속봉이 주기적으로 위치한 구조로서 Gyro-TWT의 iinteractio circuit으로 사용되기 위해서 설계되었다. 도파관에 금속봉이 주기적으로 위치한 구조의 group velocity를 측정하기 위해서 FM Reflectometry와 기존의 Network Analyzer Time Domain 기능이 사용되어졌으며, phase velocity를 측정하기위해 서 short metal plate를 이용한 방법과 High Frequency Structure Simulator (HFSS)가 이용되었다 측정된 결과는 이론치, 시뮬레이션과 비교했으며 각각의 비교는 잘 일치함을 보여 FM Reflectometry기법이 분산특성 측정에 사용되어질 수 있음을 보였다.

• 전기의세계
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• v.25 no.4
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• pp.63-67
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• 1976

A new method for simplifying linear, bilateral and passive networks is presented, and the principle employed is based upon the elimination of mutual impedance and floating nodes of the metwork by introducing incidence matrix notations and bus admittance matrices. The method suggested is, particularly, suited for machine computations and applycable for reducing the calculation time in power system short-circuit and load-flow studies with good results.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.4
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• pp.533-542
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• 1994

This paper presents the new algorithm for fault analysis and this algorithm obtains requisite term for fault analysis by the two-port network technique. Therefore, the fault calculation time is composed of only few fundamental arithmetic calculation. The graphic user environment for fault analysis is implemented in mouse-oriented user interface with window and pull-down menu. The result of the algorithm proved to be identical with the sample system in Ref.[8]. this package can be a useful tool for fault analysis.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.95-96
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• 2006

ITO thin film is generally fabricated by various methods such as spray, CVD, evaporation, electron gun deposition, direct current electroplating, high frequency sputtering, and reactive DC sputtering. However, some problems such as peaks, bumps, large particles, and pin-holes on the surface of ITO thin film were reported, which caused the destruction of color quality, the reduction of device life time, and short-circuit. Chemical mechanical polishing (CMP) process is one of the suitable solutions which could solve the problems.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1071-1072
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• 2007

인버터 출력단은 구조상 상단락의 위험성이 내재되어있기 때문에 이를 회피하기 위한 Dead time의 적용이 반드시 요구된다. 본 논문에서는 상단락 방지기능을 갖는 출력단의 구조를 사용한 파워 모듈을 설계하고 상단락 방지기능 분석 및 Q3D Extractor와 PSPICE를 사용하여 상단락 방지형 인버터의 출력단기생임피던스의 영향을 고려한 스위칭 동작 특성을 분석하였다.

• Proceedings of the KIEE Conference
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• 1999.07b
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• pp.976-978
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• 1999

Recently PWM invertor is broadly used for control of induction motor. The invertor is able to generate sin wave current from high speed switching power device such as IGBT. However the invertor is disturbed by dead time inevitably needed to prevent a short of the DC link voltage, and the dead time mainly causes distortions of the output current. In this Paper the dead time compensation method which corrects the voltage error from dead time, and Min Max algorithm enlarging the operating voltage of PWM were Proposed. This method can be implemented by software programming without any additional hardware circuit. The proposed algorithms were implemented by DSP(TMS320C31, 40MHz) and FPGA(QL2007, Quick Logic) described in VHDL. and applied to 3 phase induction motor(2.2 KW) to show the superior performance

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.265-269
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• 1994

The switching dead time avoiding a bridge leg short circuit in PWM voltage source inverter produces distortions of the controlling inverter output performance such as current waveform, voltage vector, and torque. In this paper, the influence of dead time is investigated. The on-line space voltage vector modulation method is used for current controller. It is possible to compensate dead time by space voltage vector modulation which generates additional pulse compensating voltage distortion caused by dead time. In addition, narrow pulse which is generally neglected can be compensated. All the algorithms, including field-oriented control are performed by one chip microprocessor 80C196MC and DSP TMS320C31. Experimental results probe that the proposed scheme provides a good inverter output performance.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.3
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• pp.273-280
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• 1990

To prevent the shoot-through phenomena in a PWM inverter, a short dead time is usually provided between a pair of switching transistors in the same leg of the inverter. In this approach, the amount of the dead time is designed to meet the worst case condition of the inverter transistors and the base drive elements. So, in normal cases, relatively large portion of the dead time is unnecessary and it results in an undesirablecurrent waveform distortion and generates ripple torque on the motor shaft. In this paper, a new base drive method to remove the undesirable portion of the dead time is described. The method senses the transistor on/off states to interlock the other transistor of the leg without the external dead time. Also, for the transistors of large current rating, the Darlington drive circuit is combined to the proposed method and is tested to verify the effectiveness. The experimental results of the proposed method are described and compared with those of the conventional dead time method.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.1
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• pp.88-99
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• 2007

In this paper, a novel new pulse power generator based on IGBT stacks is proposed for pulse power application. Because it can generate up to 60kV pulse output voltage without any step- up transformer or pulse forming network, it has advantages of fast rising time, easiness of pulse width variation and rectangular pulse shape. Proposed scheme consists of series connected 9 power stages to generate maximum 60kV output pulse and one series resonant power inverter to charge DC capacitor voltage. Each power stages are configured as 8 series connected power cells and each power cell generates up to 850VDC pulse. Finally pulse output voltage is applied using total 72 series connected IGBTs. To reduce component for gate power supply, a simple and robust gate drive circuit is proposed. For gating signal synchronization, full bridge invertor and pulse transformer generates on-off signals of IGBT gating with gate power simultaneously and it has very good characteristics of short circuit protection.