• Journal of the Korean Operations Research and Management Science Society
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• v.21 no.3
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• pp.47-61
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• 1996

An ATM switch must deal with various kinds of input sources having different traffic characteristics and it must guarantee very small value of cel loss probability, about 10$^{8}$ -10$^{12}$ , to deal with loss-sensitive traffics. In order to estimate such a rate event probability with simulation procedure, a variance reduction technique is essential for obtaining an appropriate level of precision with reduced cost. In this paper, we propose a hybrid simulation technique to achieve reduction of variance of cell loss probability estimator, where hybrid means the combination of analytical method and simulation procedure. A discrete time queueing model with multiple input sources and a finite shared buffer is considered, where the arrival process at an input source and a finite shared buffer is considered, where the arrival process at an input source is governed by an Interrupted Bernoulli Process and the service rate is constant. We deal with heterogeneous input sources as well as homogeneous case. The performance of the proposed hybrid simulation estimator is compared with those of the raw simulation estimator and the importance sampling estimator in terms of variance reduction ratios.

• Journal of Korea Society of Industrial Information Systems
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• v.10 no.1
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• pp.49-57
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• 2005

ATM Form has defined the guaranteed frame rate (GFR) service to provide minimum cell rate (MCR) guarantees for TCP traffic in ATM networks and allow it to fairly share residual bandwidth. GFR switch implementation consists of the frame-based generic cell rate algorithm (F-GCRA) and a frame forwarding mechanism. The F-GCRA identifies frames that are eligible for an MCR guarantee. The frame forwarding mechanism buffers cells at a frame unit according to information provided by the F-GCRA and forwards the buffered cells to an output port according to its scheduling discipline. A simple GFR mechanism with shared buffer with a global threshold is a feasible implementation mechanism, but has been known that it is insufficient to guarantee the MCR. This paper has estimated performance of GFR service for TCP traffic over ATM switches with the simple FIFO-based mechanism

• Journal of KIISE:Information Networking
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• v.30 no.3
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• pp.416-423
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• 2003

This paper proposes a continuous-time queuing model of a shared-buffer packet switch and an approximate algorithm. N arrival processes have heterogeneous busty traffic characteristics. The arrival processes are modeled by Coxian distribution with order 2 that is equivalent to Interruped Poisson Process. The service time is modeled by Erlang distribution with r stages. First the approximate algorithm performs the aggregation of N arrival processes as a single state variable. Next the algorithm discompose the queuing system into N subsystems which are represented by aggregated state variables. And the balance equations based on these aggregated state variables are solved for by iterative method. Finally the algorithm is validated by comparing the results with those of simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.80-90
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• 1996

The efficienty of ATM is based on the statical multiplexing of fixed-length packets, which are called cells. The most important technical point for realizing ATM switching network is an arrangement of the buffers and switches. Current most ATM switching networks are being achieved by using the switching modules based on the unit switch of $8{\times}8$ 150Mb/s or $16{\times}16$ 150Mb/s, the unit switch of $32{\times}32$150Mb/s for a large scale system is under study in many countries. In this paper, we proposed a new $32{\times}32$(4.9Gb/s throughput) ATM switch using Shared buffer memory switch which provides superior traffic characteristics in the cell loss, delay and throughput performance and easy LSI(Large Scale Integrated circuit). We analytically estimated and simulated by computer the buffer size into it. We also proposed the configuration of the large capacity ATM switching network($M{\times}M$.M>1,000) consisting of multistage to improve the link speed by non-blocking.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.9
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• pp.358-365
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• 2003

To support Internet traffic efficiently over ATM networks, Guaranteed Frame Rate(GFR) has been proposed in the ATM Forum. GFR provides minimum rate guarantees to VCs and allows any excess bandwidth in the network to be shared among the contending VCs in a fair manner. In this paper, we proposed a new fuzzy logic based buffer management algorithm that provides MCR guarantee and fair sharing to GFR VCs. A key feature of proposed algorithm is its ability to accept or drop a new incoming packet dynamically based on buffer condition and load ratio of VCs. This is achieved by using fuzzy logic controller for the production of a drop factor. Simulation results show that proposed scheme significantly improves fairness and TCP throughput compared with previous schemes.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.7
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• pp.22-29
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• 2002

The Gauranteed Frame Rate service category was proposed by the ATM Forum as an enhancement to the UBR service. This service aims to support minimum cell rate gaurantee for each virtual connection and allow any excess bandwidth in the network to be shared among the contending VCs in a fair manner. We propose a new buffer management algorithm for GFR service through FIFO queuing discipline. Proposed scheme can provide minimum bandwidth guarantee for GFR VCs as well as improve the fairness among the competing GFR VCs on a single FIFO queue. From simulation results, we demonstrate the proposed scheme fulfills the requirement of GFR service as well as improves the TCP throughput.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.5
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• pp.429-432
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• 2004

In this paper, we propose a new sorting algorithm for ATM switch with a shared buffer which has a sequencer architecture with single queue. The proposed switch performs a sorting procedure of ATM cell based on the output port number of ATM cell with hardware implementation. The proposed architecture has a single buffer physically but logically it has function of multi-queue which is designed at most to control the conflicts in output port. In the future, this architecture will take various applications for routing switch and has flexibility for the extension of system structure. therefore, this structure is expected on good structure in effective transmission.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1497-1501
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• 2005

Branch instructions which make the sequential instruction flow changed cause pipeline stalls in microprocessor. The pipeline hazard due to branch instructions are the most serious problem that degrades the performance of microprocessors. Branch target buffer predicts whether a branch will be taken or not and supplies the address of the next instruction on the basis of that prediction. If the hanch target buffer predicts correctly, the instruction flow will not be stalled. This leads to the better performance of microprocessor. In this paper, the architecture of a ta8 memory that branch target buffer and TLB can share is presented. Because the two tag memories used for branch target buffer and TLB each is replaced by single combined tag memory, we can expect the smaller chip size and the faster prediction. This shared tag architecture is more advantageous for the microprocessors that uses more bits of address and exploits much more instruction level parallelism.

• Journal of KIISE:Databases
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• v.36 no.5
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• pp.399-404
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• 2009

In a multiple-server DBMS using the share-disk model, when a server process updates data, the updated ones are not immediately reflected to the buffers of the other server processes. Thus, the other server processes may read invalid data. In this paper, we propose a novel method to solve this problem. In this method the server process stores the identifiers and timestamps of the pages that have been updated during a transaction into the coherency volume when the transaction commits. Then, the server process invalidates its buffers of the pages updated by the other server processes by accessing the coherency volume when the lock is acquired, and, subsequently, read the up-to-date versions of the pages from disk. This method needs only a very small coherency volume and shows a good performance because the amount of data that need to be accessed is very small.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.373-376
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• 2003

This paper presents a new, three-dimensional round-robin scheduler that provides high throughput and fair across in an advanced input-queued packet switch using shared input buffers. We consider an architecture in which each input port group shares a common buffer and maintains a separate queue for each output, which is ratted the distributed common input buffer switch. In an NxN switch, our scheduler determines which queue in the total MxN input queues is served during each time slot where M is the number of common buffers. We suppose that each common buffer has K input ports and K output ports, and manages N output queues. The 3DRR scheduler determines MxK queues in every K(M) cycle when $K\geq$M (K$\leq$M), and provides massively parallel processing for the applications of high-speed switches with a large number of ports. The 3-DRR scheduler can be implemented using duplicated simple logic components allowing very high-speed implementation.