• Journal of Power Electronics
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• v.13 no.4
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• pp.626-635
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• 2013

An analysis of the junction capacitance in resonant rectifiers which has a significant impact on the operating point of resonance circuits is studied in this paper, where the junction capacitance of the rectifier diode is to decrease the resonant current and output voltage in the circuit when compared with that in an ideal rectifier diode. This can be represented by a simplified series resonant equivalent circuit and a voltage transfer function versus the normalized operating frequency at varied values of the resonant capacitor. A low voltage to high voltage push-pull DC/DC resonant converter was used as a design example. The design procedure is based on the principle of the half bridge class-DE resonant rectifier, which ensures more accurate results. The proposed scheme provides a more systematic and feasible solution than the conventional resonant push-pull DC/DC converter analysis methodology. To increase circuit efficiency, the main switches and the rectifier diodes can be operated under the zero-voltage and zero-current switching conditions, respectively. In order to achieve this objective, the parameters of the DC/DC converter need to be designed properly. The details of the analysis and design of this DC/DC converter's components are described. A prototype was constructed with a 62-88 kHz variable switching frequency, a 12 $V_{DC}$ input voltage, a 380 $V_{DC}$ output voltage, and a rated output power of 150 W. The validity of this approach was confirmed by simulation and experimental results.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1298-1307
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• 2017

The constant on-time current-mode controlled (COT-CMC) switching dc-dc converter is stable, with no subharmonic oscillation in its current loop when a voltage ripple in its outer voltage loop is ignored. However, when its output capacitance is small or its feedback gain is high, subharmonic oscillation may occur in a COT-CMC buck converter with a proportional-integral (PI) compensator. To investigate the subharmonic instability of COT-CMC buck converters with a PI compensator, an accurate reduced-order asynchronous-switching map model of a COT-CMC buck converter with a PI compensator is established. Based on this, the instability behaviors caused by output capacitance and feedback gain are investigated. Furthermore, an approximate instability condition is obtained and design-oriented stability boundaries in different circuit parameter spaces are yielded. The analysis results show that the instability of COT-CMC buck converters with a PI compensator is mainly affected by the output capacitance, output capacitor equivalent series resistance (ESR), feedback gain, current-sensing gain and constant on-time. The study results of this paper are helpful for the circuit parameter design of COT-CMC switching dc-dc converters. Experimental results are provided to verify the analysis results.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.2
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• pp.9-17
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• 2002

A high-efficiency electronic ballast for HID lamps is presented. The ballast consists of a PFC and a resonant inverter. To reduce losses of the ballast, DC link voltage should be determined by taking into account the peak voltage of lamp and the maximum flux density should be kept 0.2[T] on all of inductors. AR inductor at bridge diode is employed in order to remove currant harmonics from PFC. An inductor is connected in series with an electrolytic capacitor at DC link to reject high-frequency current. The acoustic resonance is eliminated using the stead spectrum technique. The electronic ballast for 250[W] metal-halide discharge lamp is implemented and 96[%] efficiency, no acoustic resonance and low conducted EMI level are accomplished.

• International Journal of Advanced Culture Technology
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• v.3 no.1
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• pp.120-128
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• 2015

In this paper, Residential roof top photovoltaic system with 9.9 kW design is proposed. The system composed of 200 Watts solar array 33 panels connecting in series 10 strings and parallels 3 strings which have maximum voltage and current are 350 V and 23.8 A. The 10 kW sinusoidal grid-connected inverter with window voltage about 270-350 is selected to convert and transfer DC Power to AC Power at PCC (Point of Common Coupling) of power system following to utility standard. However the impact of fluctuation and uncertainty of weather condition of PV may decrease the voltage stability and voltage collapse of power system. In order to solve this problem the energy storage such 120 V 1200 Ah battery bank and 30 kVAR capacitor are designed for voltage stability control. The other expensed for installing the system such battery charger, cable, accessories and maintenance cost are concerned. The economic analysis by using investment from money loan with interest about 7% and use own money which loss income of deposit about 3% are calculated as 671,844 and 547,044 for PV system with energy storage and non energy storage respectively. The solar energy from PV is about 101,616 Bath per year which evaluated by using the value of $5kWh/m^2/day$ from average peak sun hour (PSH) of the Thailand and 6.96 Bath/kWh of Feed in Tariff Incentive. The payback periods of four scenarios are proposed follow as i) PV system with energy storage and use loan money is 15 years ii) PV system with no energy storage and use loan money is 10 years iii) PV system with energy storage and use deposit money is 9 years iv) PV system with energy storage and use deposit money is 7 years. In addition, the other scenarios of economic analysis such no FIT support and other type of economic analysis such NPV and IRR are proposed in this paper.

• Journal of the Korean Institute of Intelligent Systems
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• v.24 no.5
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• pp.457-461
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• 2014

Using $0.18{\mu}m$ CMOS process silicon neuron circuit of the pulse type for modeling biological neurons, were designed in the semiconductor integrated circuit. Neuron circuiSt providing is formed by MOS switch for initializing the input terminal of the capacitor to the input current signal, a pulse signal and an amplifier stage for generating an output voltage signal. Synapse circuit that can convert the current signal output of the input voltage signal, using a bump circuit consisting of NMOS transistors and PMOS few. Configure a chain of neurons for verification of the neuron model that provides synaptic neurons and two are connected in series, were performed SPICE simulation. Result of simulation, it was confirmed the normal operation of the synaptic transmission characteristics of the signal generation of nerve cells.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.14 no.6
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• pp.117-124
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• 2015

In this paper, a new kind of wideband, low-loss composite right/left-handed (CRLH) transmission line (TL) and a Wilkinson power divider are presented. The TL is composed of a parallel meander inductor and a series cutting capacitor based on coplanar waveguide (CPW) structure. The power divider is designed by substituting the CRLH-TL into the conventional transmission line. The experiment results show that the TL has a good agreement with the desired results, exhibiting the return losses under 12 dB from 8.4 GHz to 34.4 GHz. The operating frequencies of the power divider are 12.05 GHz to 13.15 GHz and 16.50 GHz to 19.30 GHz, respectively. The 20 dB bandwidths are 8.9 % and 17.9 %, respectively. Typical experimental measurements are conducted and compared with the simulated results.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.7-11
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• 2007

This paper presents a multiband octa-phase LC VCO for SDR receiver. Four identical LC VCOs are connected by using series coupling transistor to obtain the octa-phase signal and low phase noise characteristic. For a multiband application, a band tuning circuit that consists of a switch capacitor circuit and two MOS varactors is proposed. As the MOS switch is on/off state, the frequency range will be varied. In addition, two varactors make the VCO be immune to process variation of the oscillation frequency. The VCO is designed in 0.18-um CMOS technology, consumes 12mA current from 1.8V supply voltage and operates with a frequency band from 885MHz to 1.342GHz (41% tuning range). As driving sub-harmonic mixer, the proposed VCO covers 3 standards(CDMA 2000 1x, WCDMA, WiBro). The measured phase noise is -105dBc@100kHz, -115dBc@1MHz, -130dBc@10MHz for CDMA 2000 1x, WCDMA, WiBro respectively.

• Journal of Electrical Engineering and Technology
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• v.8 no.2
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• pp.252-261
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• 2013

In this paper, a nonlinear adaptive damping controller based on radial basis function neural network (RBFNN), which can infinitely approximate to nonlinear system, is proposed for thyristor controlled series capacitor (TCSC). The proposed TCSC adaptive damping controller can not only have the characteristics of the conventional PID, but adjust the parameters of PID controller online using identified Jacobian information from RBFNN. Hence, it has strong adaptability to the variation of the system operating condition. The effectiveness of the proposed controller is tested on a two-machine five-bus power system and a four-machine two-area power system under different operating conditions in comparison with the lead-lag damping controller tuned by evolutionary algorithm (EA). Simulation results show that the proposed damping controller achieves good robust performance for damping the low frequency oscillations under different operating conditions and is superior to the lead-lag damping controller tuned by EA.

• ETRI Journal
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• v.42 no.5
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• pp.781-789
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• 2020

In this study, an E-band low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) has been designed using silicon-germanium 130-nm bipolar complementary metal-oxide-semiconductor technology to suppress unwanted signal gain outside operating frequencies and improve the signal gain and noise figures at operating frequencies. The proposed impedance-controllable filter has series (R_s) and parallel (R_p) resistors instead of a conventional inductor-capacitor (L-C) filter without any resistor in an interstage matching circuit. Using the impedance-controllable filter instead of the conventional L-C filter, the unwanted high signal gains of the designed E-band LNA at frequencies of 54 GHz to 57 GHz are suppressed by 8 dB to 12 dB from 24 dB to 26 dB to 12 dB to 18 dB. The small-signal gain S₂₁ at the operating frequencies of 70 GHz to 95 GHz are only decreased by 1.4 dB to 2.4 dB from 21.6 dB to 25.4 dB to 19.2 dB to 24.0 dB. The fabricated E-band LNA MMIC with the proposed filter has a measured S₂₁ of 16 dB to 21 dB, input matching (S₁₁) of -14 dB to -5 dB, and output matching (S₂₂) of -19 dB to -4 dB at E-band operating frequencies of 70 GHz to 95 GHz.

• Journal of Electrical Engineering and Technology
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• v.5 no.2
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• pp.179-190
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• 2010

This paper describes a new stochastic heuristic algorithm in engineering problem optimization especially in power system applications. An improved particle swarm optimization (PSO) called adaptive particle swarm optimization (APSO), mixed with simulated annealing (SA), is introduced and referred to as APSO-SA. This algorithm uses a novel PSO algorithm (APSO) to increase the convergence rate and incorporate the ability of SA to avoid being trapped in a local optimum. The APSO-SA algorithm efficiency is verified using some benchmark functions. This paper presents the application of APSO-SA to find the optimal location, type and size of flexible AC transmission system devices. Two types of FACTS devices, the thyristor controlled series capacitor (TCSC) and the static VAR compensator (SVC), are considered. The main objectives of the presented method are increasing the voltage stability index and over load factor, decreasing the cost of investment and total real power losses in the power system. In this regard, two cases are considered: single-type devices (same type of FACTS devices) and multi-type devices (combination of TCSC, SVC). Using the proposed method, the locations, type and sizes of FACTS devices are obtained to reach the optimal objective function. The APSO-SA is used to solve the above non.linear programming optimization problem for better accuracy and fast convergence and its results are compared with results of conventional PSO. The presented method expands the search space, improves performance and accelerates to the speed convergence, in comparison with the conventional PSO algorithm. The optimization results are compared with the standard PSO method. This comparison confirms the efficiency and validity of the proposed method. The proposed approach is examined and tested on IEEE 14 bus systems by MATLAB software. Numerical results demonstrate that the APSO-SA is fast and has a much lower computational cost.