• Title/Summary/Keyword: Sequence impedance

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A Study on Battery Simulator Including Aging and Dynamic Impedance Model (노화 및 동특성 임피던스 모델을 포함한 배터리 시뮬레이터에 관한 연구)

  • Lee, Jong-Hak;Kim, Soo-Bin;Oh, Sang-Keun;Song, Seung-Ho
    • The Transactions of the Korean Institute of Power Electronics
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    • v.25 no.3
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    • pp.171-180
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    • 2020
  • This paper presents the implementation and control methods of a battery simulator. The proposed battery simulator can emulate the dynamic characteristics of any actual battery using the second RC ladder model of the equivalent circuit. Moreover, it can emulate the variation of impedance, which is the result of the change of battery characteristics due to the aging effect. The parameters of the battery simulator can be derived from the sequence of tests of the actual battery or only from the data supplied by the battery manufacturer. Proposed methods for the battery simulator are tested by extensive experiments. Test results show that the proposed battery simulator can emulate not only the dynamic characteristics but also the aging effects of the actual battery in real time.

Anti-islanding Detection of Photovoltaic Inverter Based on Negative Sequence Voltage Injection to Grid (역상분 전압 주입을 이용한 태양광 인버터의 단독 운전 검출)

  • Kim, Byeong-Heon;Park, Yong-Soon;Sul, Seung-Ki;Kim, Woo-Chull;Lee, Hyun-Young
    • The Transactions of the Korean Institute of Power Electronics
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    • v.17 no.6
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    • pp.546-552
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    • 2012
  • This paper presents an active anti-islanding detection method using negative sequence voltage injection to the grid through a three-phase photovoltaic inverters. Because islanding operation mode can cause a variety of problems, the islanding detection of grid-connected photovoltaic inverter is the mandatory feature. The islanding mode is detected by measuring the magnitude of negative sequence impedance calculated by the negative sequence voltage and current at the point of common coupling. Simulation and experimental test are performed to verify the effectiveness of the proposed method which can detect the islanding mode in the specified time. The test has been done in accordance with the condition on IEEE Std 929-2000.

The Real-Time Distance Relay Algorithm Using fault Location Estimation Information for Parallel Transmission Line (병행 2회선 송전선로에서 고장점 위치 추정정보를 이용한 실시간 거리계전 알고리즘)

  • 이재규;유석구
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.52 no.3
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    • pp.183-192
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    • 2003
  • This paper presents the real-time implemented distance relay algorithm which the fault distance is estimated with only local terminal information. When a single-phase-to-earth fault on a two-parallel transmission line occurs, the reach accuracy of distance relay is considerably affected by the unknown variables which are fault resistance, fault current at the fault point and zero- sequence current of sound line The zero-sequence current of sound line is estimated by using the zero sequence voltage which is measured by relaying location Also. the fault resistance is removed at the Process of numerical formula expansion. Lastly, the fault current through a fault point is expressed as a function of the zero-sequence current of fault line, zero-sequence current of sound line, and line, and fault distance. Therefore, the fault phase voltage can be expressed as the quadratic equation of the fault distance. The solution of this Quadratic equation is obtained by using a coefficient of the modified quadratic equation instead of using the square root solution method. After tile accurate fault distance is estimated. the mote accurate impedance is measured by using such an information.

Resonance Investigation and Active Damping Method for VSC-HVDC Transmission Systems under Unbalanced Faults

  • Tang, Xin;Zhan, Ruoshui;Xi, Yanhui;Xu, Xianyong
    • Journal of Power Electronics
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    • v.19 no.6
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    • pp.1467-1476
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    • 2019
  • Grid unbalanced faults can cause core saturation of power transformer and produce lower-order harmonics. These issues increase the electrical stress of power electronic devices and can cause a tripping of an entire HVDC system. In this paper, based on the positive-sequence and negative-sequence impedance model of a VSC-HVDC system as seen from the point of common connection (PCC), the resonance problem is analyzed and the factors determining the resonant frequency are obtained. Furthermore, to suppress over-voltage and over-current during resonance, a novel method using a virtual harmonic resistor is proposed. The virtual harmonic resistor emulates the role of a resistor connected in series with the commutating inductor without influencing the active and reactive power control. Simulation results in PSCAD/EMTDC show that the proposed control strategy can suppress resonant over-voltage and over-current. In addition, it can be seen that the proposed strategy improves the safety of the VSC-HVDC system under unbalanced faults.

A 1.88-mW/Gb/s 5-Gb/s Transmitter with Digital Impedance Calibration and Equalizer (디지털 임피던스 보정과 이퀄라이저를 가진 1.88mW/Gb/s 5Gb/s 송신단)

  • Kim, Ho-Seong;Beak, Seung-Wuk;Jang, Young-Chan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.1
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    • pp.110-116
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    • 2016
  • This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.

Fault Location and Classification of Combined Transmission System: Economical and Accurate Statistic Programming Framework

  • Tavalaei, Jalal;Habibuddin, Mohd Hafiz;Khairuddin, Azhar;Mohd Zin, Abdullah Asuhaimi
    • Journal of Electrical Engineering and Technology
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    • v.12 no.6
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    • pp.2106-2117
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    • 2017
  • An effective statistical feature extraction approach of data sampling of fault in the combined transmission system is presented in this paper. The proposed algorithm leads to high accuracy at minimum cost to predict fault location and fault type classification. This algorithm requires impedance measurement data from one end of the transmission line. Modal decomposition is used to extract positive sequence impedance. Then, the fault signal is decomposed by using discrete wavelet transform. Statistical sampling is used to extract appropriate fault features as benchmark of decomposed signal to train classifier. Support Vector Machine (SVM) is used to illustrate the performance of statistical sampling performance. The overall time of sampling is not exceeding 1 1/4 cycles, taking into account the interval time. The proposed method takes two steps of sampling. The first step takes 3/4 cycle of during-fault and the second step takes 1/4 cycle of post fault impedance. The interval time between the two steps is assumed to be 1/4 cycle. Extensive studies using MATLAB software show accurate fault location estimation and fault type classification of the proposed method. The classifier result is presented and compared with well-established travelling wave methods and the performance of the algorithms are analyzed and discussed.

A Study On The Characteristics Of The Medium Voltage Power Distribution Line Channel By Wideband Channel Impulse Response Measurement Using PN Sequence (PN 시퀀스 방식의 광대역 임펄스 응답 측정을 통한 고압 배전선로 채널 특성 연구)

  • Oh Hui-Myoung;Choi Sung-Soo;Lee Jae-Jo;Kim Kwan-Ho;Whang Keum-Chan
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.54 no.1
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    • pp.56-60
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    • 2005
  • In the power-line communication(PLC) systems, the power line is a wired medium. However, the power line channel has the multi-path fading characteristics like the wireless channel in the wireless communication systems because it has the signal reflection and divergence by the impedance mismatching between many branch lines and loads. So the analysis of the multi-path characteristics is very important, and it has been doing by the several measurement methods for the impulse response between the transmitter and the receiver. PN sequence method has originally been used as a wideband impulse response measurement mettled for wireless channel, but it is recently being applied to not only the wireless channel but also the wired channel like the power line channel. This method is more useful and effective for the long distance communication channel like the medium voltage power distribution line with the multi-paths[1]. In this thesis, we have measured impulse response for the medium voltage power distribution line channel by the wideband measurement method using PN sequence, analytically studied the measured data and presented the results.

A Study on the Technique of Fault Classification in Transmission Lines Using a Combined Adaptive Network-Based Fuzzy Inference System (ANFIS를 이용한 송전선로의 고장판별 기법에 관한 연구)

  • Yeo, Sang-Min;Kim, Cheol-Hwan
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.50 no.9
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    • pp.417-423
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    • 2001
  • This paper proposes a technique for fault detection and classification for both LIF(Low Impedance Fault)s and HIF(High Impedance Fault)s using Adaptive Network-based Fuzzy Inference System(ANFIS). The inputs into ANFIS are current signals only based on Root-Mean-Square(RMS) values of 3-phase currents and zero sequence current. The performance of the proposed technique is tested on a typical 154 kV Korean transmission line system under various fault conditions. Test results show that the ANFIS can detect and classily faults including (LIFs and HIFs) accurately within half a cycle.

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An Algorithm of fault Location Technique for Long Transmission Line (송전선로의 고장점 표정 알고리즘)

  • Park, C.W.;Kim, S.R.;Shin, M.C.;Nam, S.B.;Lee, B.K.
    • Proceedings of the KIEE Conference
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    • 2002.07a
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    • pp.145-147
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    • 2002
  • In this paper, the improved fault locating method using distributed parameter which calculating the reduced voltage and current according to the ground capacitance in long transmission line was proposed. For the purpose of the fault locating algorithm non influenced source impedance, the loop method was used in the system modeling analysis. To enhance the fault locating, zero sequence of the fault current which is variable according to ground capacitance was not used but positive and negative sequence. System model was simulated using EMTP software. To verify the accuracy of proposed method, in different cases 64 sampled data per cycle was used and 160km and 300km long transmission line has fault resistance $0{\Omega}\;and\;100{\Omega}$ respectively was compared.

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The Design of Lumped Constant Circuit for the Simulation of A Real 22.9 kV-y Distribution Line (22.9 kV-y 실긍장 배전선로 모의를 위한 집중정수회로의 설계)

  • Yun, Chul-Ho;Jeong, Yeong-Ho;Han, Yong-Huei
    • Proceedings of the KIEE Conference
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    • 1999.07c
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    • pp.1186-1188
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    • 1999
  • When we perform the test related to the power distribution system such as artificial fault test, protective coordination test, distribution automation test in short length test line, Lumped Constant Circuit, a kind of variable impedance, should be attached to the test line in order to make it equivalent to a real line in length electrically. In this paper we designed the positive sequence and zero sequence Lumped Constant Circuit with optimized inductor and resister for the modification of long, 16km, distribution line, when they are attached to the short, 4km, distribution test line.

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