• 제목/요약/키워드: Semiconductor layer

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Al 박막이 증착 된 Si(111) 기판 위에 HVPE 방법으로 성장한 GaN의 특성 (The Properties of GaN Grown by BVPE Method on the Si(111) Substrate with Pre-deposited Al Layer)

  • 신대현;백신영;이창민;이삼녕;강남룡;박승환
    • 한국진공학회지
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    • 제14권4호
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    • pp.201-206
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    • 2005
  • 본 연구에서는 HVPE (Hydride Vapor Phase Epitaxy) 방법으로 Si 위에 GaN/AIN/Al/Si 구조를 제작하고, AlN 버퍼층의 두께에 따른 광학적 특성을 조사함으로써 효과적인 eaN 성장을 위한HVPE에서의 공정 방법을 개선하고자 하였다. 이를 위해 Al을 증착한 Si 기판과 그렇지 않은 경우를 PL측정을 통해 그 효과를 관찰하였고, $5{\AA}$ 두께의 Al 대해 AlN 버퍼층의 두께를 변화시켜가면서 GaN를 성장시켜 그 특성을 조사하였다. Al을 증착한 경우가 증착하지 않은 경우에 비해 광학적 특성이 우수한 것으로 나타났으며, AlN의 두께 변화에 대해서는 양질의 GaN를 얻기 위한 최적의 두께는 약 $260{\AA}$ 인 것으로 나타났다. 이 경우 SEM을 이용한 표면사진에서 GaN의 초기성장이 hexagonal형태로 성장되고 있음을 관찰할 수 있었다. 또한 XRD의 회절 패턴은 GaN가 {0001} 방향으로 우선 배향성을 가지고 성장되고 있음을 보여주고 있었다.

High Performance ESD/Surge Protection Capability of Bidirectional Flip Chip Transient Voltage Suppression Diodes

  • Pharkphoumy, Sakhone;Khurelbaatar, Zagarzusem;Janardhanam, Valliedu;Choi, Chel-Jong;Shim, Kyu-Hwan;Daoheung, Daoheung;Bouangeun, Bouangeun;Choi, Sang-Sik;Cho, Deok-Ho
    • Transactions on Electrical and Electronic Materials
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    • 제17권4호
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    • pp.196-200
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    • 2016
  • We have developed new electrostatic discharge (ESD) protection devices with, bidirectional flip chip transient voltage suppression. The devices differ in their epitaxial (epi) layers, which were grown by reduced pressure chemical vapor deposition (RPCVD). Their ESD properties were characterized using current-voltage (I-V), capacitance-voltage (C-V) measurement, and ESD analysis, including IEC61000-4-2, surge, and transmission line pulse (TLP) methods. Two BD-FCTVS diodes consisting of either a thick (12 μm) or thin (6 μm), n-Si epi layer showed the same reverse voltage of 8 V, very small reverse current level, and symmetric I-V and C-V curves. The damage found near the corner of the metal pads indicates that the size and shape of the radius governs their failure modes. The BD-FCTVS device made with a thin n- epi layer showed better performance than that made with a thick one in terms of enhancement of the features of ESD robustness, reliability, and protection capability. Therefore, this works confirms that the optimization of device parameters in conjunction with the doping concentration and thickness of epi layers be used to achieve high performance ESD properties.

솔더볼 배치에 따른 절연층 재료가 WLCSP 신뢰성에 미치는 영향 (The Effect of Insulating Material on WLCSP Reliability with Various Solder Ball Layout)

  • 김종훈;양승택;서민석;정관호;홍준기;변광유
    • 마이크로전자및패키징학회지
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    • 제13권4호
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    • pp.1-7
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    • 2006
  • WLCSP(wafer level chip size package)는 웨이퍼 레벨에서 패키지 공정이 이루어지는 차세대 패키지 중 하나이다. WLCSP는 웨이퍼 레벨에서 패키지 공정이 이루어진다는 특징으로 인하여 웨이퍼당 생산되는 반도체 칩의 수에 따라 그 패키징 비용을 크게 줄일 수 있다는 장점이 있다. 그러나 응력 버퍼 역할을 하는 기판을 없애는 혁신적인 구조로 인하여 솔더 조인트의 신뢰성이 기존의 BGA 패키지에 비하여 취약하게 되는데, 이러한 솔더 조인트 신뢰성에 대하여 반도체 칩과 솔더볼을 연결하는 폴리머 절연층은 열팽창계수 차이에 의해 발생하는 응력을 흡수하는 중요한 역할을 하게 된다. 본 연구에서는 하이닉스에서 개발한 Omega-CSP를 사용하여 솔더볼 배열 변화와 제 1 절연층의 특성에 따른 솔더 조인트의 열피로 특성을 평가하였다. 그 결과 절연층의 특성 변화가 솔더 조인트의 열피로 특성에 주는 영향은 솔더볼 배열 구조에 따라 변화되는 것을 확인하였다.

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A Study on Modified Silicon Surface after $CHF_3/C_2F_6$ Reactive Ion Etching

  • Park, Hyung-Ho;Kwon, Kwang-Ho;Lee, Sang-Hwan;Koak, Byung-Hwa;Nahm, Sahn;Lee, Hee-Tae;Kwon, Oh-Joon;Cho, Kyoung-Ik;Kang, Young-Il
    • ETRI Journal
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    • 제16권1호
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    • pp.45-57
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    • 1994
  • The effects of reactive ion etching (RIE) of $SiO_2$ layer in $CHF_3/C_2F_6$ on the underlying Si surface have been studied by X-ray photoelectron spectroscopy (XPS), secondary ion mass spectrometer, Rutherford backscattering spectroscopy, and high resolution transmission electron microscopy. We found that two distinguishable modified layers are formed by RIE : (i) a uniform residue surface layer of 4 nm thickness composed entirely of carbon, fluorine, oxygen, and hydrogen with 9 different kinds of chemical bonds and (ii) a contaminated silicon layer of about 50 nm thickness with carbon and fluorine atoms without any observable crystalline defects. To search the removal condition of the silicon surface residue, we monitored the changes of surface compositions for the etched silicon after various post treatments as rapid thermal anneal, $O_2$, $NF_3$, $SF_6$, and $Cl_2$ plasma treatments. XPS analysis revealed that $NF_3$ treatment is most effective. With 10 seconds exposure to $NF_3$ plasma, the fluorocarbon residue film decomposes. The remained fluorine completely disappears after the following wet cleaning.

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항온항습 환경에 노출된 Al2O3 ALD 박막의 특성 평가 (Characteristics Evaluation of Al2O3 ALD Thin Film Exposed to Constant Temperature and Humidity Environment)

  • 김현우;송태민;이형준;전용민;권정현
    • 반도체디스플레이기술학회지
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    • 제21권2호
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    • pp.11-14
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    • 2022
  • In this work, we evaluated the Al2O3 film, which was deposited by atomic layer deposition, degraded by exposure to harsh environments. The Al2O3 films deposited by atomic layer deposition have long been used as a gas diffusion barrier that satisfies barrier requirements for device reliability. To investigate the barrier and mechanical performance of the Al2O3 film with increasing temperature and relative humidity, the properties of the degraded Al2O3 film exposed to the harsh environment were evaluated using electrical calcium test and tensile test. As a result, the water vapor transmission rate of Al2O3 films stored in harsh environments has fallen to a level that is difficult to utilize as a barrier film. Through water vapor transmission rate measurements, it can be seen that the water vapor transmission rate changes can be significant, and the environment-induced degradation is fatal to the Al2O3 thin films. In addition, the surface roughness and porosity of the degraded Al2O3 are significantly increased as the environment becomes severer. the degradation of elongation is caused by the stress concentration at valleys of rough surface and pores generated by the harsh environment. Becaused the harsh envronment-induced degradation convert amorphous Al2O3 to crystalline structure, these encapsulation properties of the Al2O3 film was easily degraded.

Y2SiO5:Eu3+ 형광체 기반 적색 전계 발광 소자 (Red-emissive Y2SiO5:Eu3+ Phosphor-based Electroluminescence Device)

  • 정현지;박순호;김종수;허 훈
    • 반도체디스플레이기술학회지
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    • 제22권1호
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    • pp.83-87
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    • 2023
  • Y2SiO5 Powder based on silicon and yttrium is well known as powder phosphors due to their excellent sustainability and efficiency. A new electroluminescence device was fabricated with Y2SiO5:Eu3+ powder phosphors though a simple screen printing method. The powder-dispersed electroluminescence device consisted of the Y2SiO5:Eu3+ powder-dispersed phosphor layer and BaTiO3-dispersed dielectric layer. The annealing temperature of the phosphor for the best powder electroluminescence performance was optimized to high temperature in ambient atmosphere though a solid-state reaction. The Eu3+ concentration for the best device performance was also investigated and furthermore, the thermal dependence of the electroluminescence intensity was investigated at the operating voltage at 100℃, which is the Curie temperature of the BaTiO3 layer. And the intensity was exponentially increased with voltage and increased linearly with frequency.

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대면적 UV 임프린팅 공정에서 잔류층 두께 예측 (Prediction of Residual Layer Thickness of Large-area UV Imprinting Process)

  • 김국원
    • 반도체디스플레이기술학회지
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    • 제12권2호
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    • pp.79-84
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    • 2013
  • Nanoimprint lithography (NIL) is the next generation photolithography process in which the photoresist is dispensed onto the substrate in its liquid form and then imprinted and cured into a desired pattern instead of using traditional optical system. There have been considerable attentions on NIL due to its potential abilities that enable cost-effective and high-throughput nanofabrication to the display device and semiconductor industry. Although one of the current major research trends of NIL is large-area patterning, the technical difficulties to keep the uniformity of the residual layer become severer as the imprinting area increases more and more. In this paper, with the rolling type imprinting process, a mold, placed upon the $2^{nd}$ generation TFT-LCD glass sized substrate($370{\times}470mm^2$), is rolled by a rubber roller to achieve a uniform residual layer. The prediction of residual layer thickness of the photoresist by rolling of the rubber roller is crucial to design the rolling type imprinting process, determine the rubber roller operation conditions-mpressing force & feeding speed, operate smoothly the following etching process, and so forth. First, using the elasticity theory of contact problem and the empirical equation of rubber hardness, the contact length between rubber roller and mold is calculated with consideration of the shape and hardness of rubber roller and the pressing force to rubber roller. Next, using the squeeze flow theory to photoresist flow, the residual layer thickness of the photoresist is calculated with information of the viscosity and initial layer thickness of photoresist, the shape of mold pattern, feeding speed of rubber roller, and the contact length between rubber roller and mold previously calculated. Last, the effects of rubber roller operation conditions, impressing force & feeding speed, on the residual layer thickness are analyzed with consideration of the shape and hardness of rubber roller.

Study of Via-Typed Air-Gap for Logic Devices Applications below 45 nm Node

  • Kim, Sang-Yong;Kim, Il-Soo;Jeong, Woo-Yang
    • Transactions on Electrical and Electronic Materials
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    • 제12권4호
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    • pp.131-134
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    • 2011
  • Back-end-of-line using ultra low-k (ULK; k < 2.5) has been required to reduce resistive capacitance beyond 45 nmtechnologies, because micro-processing units need higher speed and density. There are two strategies to manufacture ULK inter-layer dielectric (ILD) materials using an air-gap (k = 1). The former ULK and calcinations of ILD degrade the mechanical strength and induce a high cost due to the complication of following process, such as chemical mechanical polishing and deposition of the barrier metal. In contrast, the air-gap based low-k ILD with a relatively higher density has been researched on the trench-type with activity, but it has limited application to high density devices due to its high air-gap into the next metal layer. The height of air-gap into the next metal layer was reduced by changing to the via-typed air-gap, up to about 50% compared to that of the trench-typed air-gap. The controllable ULK was easily fabricated using the via-typed air-gap. It is thought that the via-type air-gap made the better design margin like via-patterning in the area with the dense and narrow lines.

High-performance thin-film transistor with a novel metal oxide channel layer

  • Son, Dae-Ho;Kim, Dae-Hwan;Kim, Jung-Hye;Sung, Shi-Joon;Jung, Eun-Ae;Kang, Jin-Kyu
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2009년도 제38회 동계학술대회 초록집
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    • pp.222-222
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    • 2010
  • Transparent semiconductor oxide thin films have been attracting considerable attention as potential channel layers in thin film transistors (TFTs) owing to their several advantageous electrical and optical characteristics such as high mobility, high stability, and transparency. TFTs with ZnO or similar metal oxide semiconductor thin films as the active layer have already been developed for use in active matrix organic light emitting diode (AMOLED). Of late, there have been several reports on TFTs fabricated with InZnO, AlZnSnO, InGaZnO, or other metal oxide semiconductor thin films as the active channel layer. These newly developed TFTs were expected to have better electrical characteristics than ZnO TFTs. In fact, results of these investigations have shown that TFTs with the new multi-component material have excellent electrical properties. In this work, we present TFTs with inverted coplanar geometry and with a novel HfInZnO active layer co-sputtered at room temperature. These TFTs are meant for use in low voltage, battery-operated mobile and flexible devices. Overall, the TFTs showed good performance: the low sub-threshold swing was low and the $I_{on/off}$ ratio was high.

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반도체 소자용 산화하프늄 기반 강유전체의 원자층 증착법 리뷰 (Review on Atomic Layer Deposition of HfO2-based Ferroelectrics for Semiconductor Devices)

  • 이영환;권태규;박민혁
    • 한국표면공학회지
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    • 제55권5호
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    • pp.247-260
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    • 2022
  • Since the first report on ferroelectricity in Si-doped hafnia (HfO2), this emerging ferroelectrics have been considered promising for the next-generation semiconductor devices with their characteristic nonvolatile data storage. The robust ferroelectricity in the sub-10-nm thickness regime has been proven by numerous research groups. However, extending their scalability below the 5 nm thickness with low temperature processes compatible with the back-end-of-line technology. In this review, therefore, the current status, technical issues, and their potential solutions of atomic layer deposition (ALD) of HfO2-based ferroelectrics are comprehensively reviewed. Several technical issues in the physical scaling of the ferroelectric thin films and potential solutions including advanced ALD techniques including discrete feeding ALD, atomic layer etching, and area selective ALD are introduced.