• Title/Summary/Keyword: Semiconductor etching process

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Abatement of CF4 Using RF Plasma with Annular Shape Electrodes Operating at Low Pressure (환상형상 전극구조를 갖는 저압 RF plasma를 이용한 CF4 제거)

  • Lee, Jae-Ok;Hur, Min;Kim, Kwan-Tae;Lee, Dae-Hoon;Song, Young-Hoon;Lee, Sang-Yun;Noh, Myung-Keun
    • Journal of Korean Society for Atmospheric Environment
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    • v.26 no.6
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    • pp.690-696
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    • 2010
  • Abatement of perfluorocompounds (PFCs) used in semiconductor and display industries has received an attention due to the increasingly stricter regulation on their emission. In order to meet this circumstance, we have developed a radio frequency (RF) driven plasma reactor with multiple annular shaped electrodes, characterized by an easy installment between a processing chamber and a vacuum pump. Abatement experiment has been performed with respect to $CF_4$, a representative PFCs widely used in the plasma etching process, by varying the power, $CF_4$ and $O_2$ flow rates, $CF_4$ concentration, and pressure. The influence of these variables on the $CF_4$ abatement was analyzed and discussed in terms of the destruction & removal efficiency (DRE), measured with a Fourier transform infrared (FTIR) spectrometer. The results revealed that DRE was enhanced with the increase in the discharge power and pressure, but dropped with the $CF_4$ flow rate and concentration. The addition of small quantity of $O_2$ lead to the improvement of DRE, which, however, leveled off and then decreased with $O_2$ flow rate.

Micro-gap DBD Plasma and Its Applications

  • Zhang, Zhitao;Liu, Cheng;Bai, Mindi;Yang, Bo;Mao, Chengqi
    • Journal of the Speleological Society of Korea
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    • no.76
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    • pp.37-42
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    • 2006
  • The Dielectric Barrier Discharge (DBD) is a nonequilibrium gas discharge that is generated in the space between two electrodes, which are separated by an insulating dielectric layer. The dielectric layer can be put on either of the two electrodes or be inserted in the space between two electrodes. If an AC or pulse high voltage is applied to the electrodes that is operated at applied frequency from 50Hz to several MHz and applied voltages from a few to a few tens of kilovolts rms, the breakdown can occur in working gas, resulting in large numbers of micro-discharges across the gap, the gas discharge is the so called DBD. Compared with most other means for nonequilibrium discharges, the main advantage of the DBD is that active species for chemical reaction can be produced at low temperature and atmospheric pressure without the vacuum set up, it also presents many unique physical and chemical process including light, heat, sound and electricity. This has led to a number of important applications such as ozone synthesizing, UV lamp house, CO2 lasers, et al. In recent years, due to its potential applications in plasma chemistry, semiconductor etching, pollution control, nanometer material and large area flat plasma display panels, DBD has received intensive attention from many researchers and is becoming a hot topic in the field of non-thermal plasma.

Study of the Reliability Characteristics of the ONON(oxide-nitride-oxide-nitride) Inter-Poly Dielectrics in the Flash EEPROM cells (플래시 EEPROM 셀에서 ONON(oxide-nitride-oxide-nitride) Inter-Poly 유전체막의 신뢰성 연구)

  • Shin, Bong-Jo;Park, Keun-Hyung
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.10
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    • pp.17-22
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    • 1999
  • In this paper, the results of the studies about a new proposal where the ONON(oxide-nitride-oxide-nitride) layer instead of the conventional ONO(oxide-nitride-oxide) layer is used as the IPD(inter-poly-dielectrics) layer to improve the data retention problem in the Flash EEPROM cell, have been discussed. For these studies, the stacked-gate Flash EEPROM cell with an about 10nm thick gate oxide and on ONO or ONON IPD layer have been fabricated. The measurement results have shown that the data retention characteristics of the devices with the ONO IPD layer are significantly degraded with an activation energy of 0.78 eV. which is much lower than the minimum value (1.0 eV) required for the Flash EEPROM cell. This is believed to be due to the partial or whole etching of the top oxide of the IPD layer during the cleaning process performed just prior to the dry oxidation process to grow the gate oxide of the peripheral MOSFET devices. Whereas the data retention characteristics of the devices with the ONON IPD layer have been found to be much (more than 50%) improved with an activation energy of 1.10 eV. This must be because the thin nitride layer on the top oxide layer in the ONON IPD layer protected the top oxide layer from being etched during the cleaning process.

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Fabrication and characterization of $WSi_2$ nanocrystals memory device with $SiO_2$ / $HfO_2$ / $Al_2O_3$ tunnel layer

  • Lee, Hyo-Jun;Lee, Dong-Uk;Kim, Eun-Kyu;Son, Jung-Woo;Cho, Won-Ju
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.134-134
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    • 2011
  • High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

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Structural characterization of $Al_2O_3$ layer coated with plasma sprayed method (플라즈마 스프레이 방법으로 코팅 된 $Al_2O_3$막의 구조적 특성)

  • Kim, Jwa-Yeon;Yu, Jae-Keun;Sul, Yong-Tae
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.16 no.3
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    • pp.116-120
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    • 2006
  • We have investigated plasma spray coated $Al_2O_3$ layers on Al-60 series substrates for development of wafer electrostatic chuck in semiconductor dry etching system. Samples were prepared without/with cooling bar on backside of samples, at various distances, and with different powder feed rates. There were many cracks and pores in the $Al_2O_3$ layers coated on Al-60 series substrates without cooling bar on the backside of samples. But the cracks and pores were almost disappeared in the $Al_2O_3$ layers on Al-60 series substrates coated with cooling bar on the back side of samples, 15 g/min. powder feed rate and various 60, 70, 80 mm working distances. Then the surface morphology was not changed with various working distances of 60, 70, 80 mm. When the powder feed rate was changed from 15 g/min to 20 g/min, the crack did not appear, but few pores appeared. Also the $Al_2O_3$ layer was coated with many small splats compared with $Al_2O_3$ layer coated with 15 g/min powder feed rate. The deposited rate of $Al_2O_3$ layer was higher when the process was done without cooling bar on the back side of sample than that with cooling bar on the back side of sample.

Robust Design for Showerhead Thermal Deformation

  • Gong, Dae-Wi;Kim, Ho-Jun;Lee, Seung-Mu;Won, Je-Hyeong
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.150.1-150.1
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    • 2014
  • Showerhead is used as a main part in the semiconductor equipment. The face plate flatness should remain constant and the cleaning performance must be gained to keep the uniformity level of etching or deposition in chemical vapor deposition process. High operating temperature or long period of thermal loading could lead the showerhead to be deformed thermally. In some case, the thermal deformation appears very sensitive to showerhead performance. This paper describes the methods for robust design using computational fluid dynamics. To reveal the influence of the post distribution on flow pattern in the showerhead cavity, numerical simulation was performed for several post distributions. The flow structure appears similar to an impinging flow near a centered baffle in showerhead cavity. We took the structure as an index to estimate diffusion path. A robust design to reduce the thermal deformation of showerhead can be achieved using post number increase without ill effect on flow. To prevent the showerhead deformation by heat loading, its face plate thickness was determined additionally using numerical simulation. The face plate has thousands of impinging holes. The design key is to keep pressure drop distribution on the showerhead face plate with the holes. This study reads the methodology to apply to a showerhead hole design. A Hagen-Poiseuille equation gives the pressure drop in a fluid flowing through such hole. The assumptions of the equation are the fluid is viscous-incompressible and the flow is laminar fully developed in a through hole. An equation can be expressed with radius R and length L related to the volume flow rate Q from the Hagen-Poiseuille equation, $Q={\pi}R4{\Delta}p/8{\mu}L$, where ${\mu}$ is the viscosity and ${\Delta}p$ is the pressure drop. In present case, each hole has steps at both the inlet and the outlet, and the fluid appears compressible. So we simplify the equation as $Q=C(R,L){\Delta}p$. A series of performance curves for a through hole with geometric parameters were obtained using two-dimensional numerical simulation. We obtained a relation between the hole diameter and hole length from the test cases to determine hole diameter at fixed hole length. A numerical simulation has been performed as a tool for enhancing showerhead robust design from flow structure. Geometric parameters for the design were post distribution and face plate thickness. The reinforced showerhead has been installed and its effective deposition profile is being shown in factory.

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Characteristics of InGaAs/GaAs/AlGaAs Double Barrier Quantum Well Infrared Photodetectors

  • Park, Min-Su;Kim, Ho-Seong;Yang, Hyeon-Deok;Song, Jin-Dong;Kim, Sang-Hyeok;Yun, Ye-Seul;Choe, Won-Jun
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.324-325
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    • 2014
  • Quantum wells infrared photodetectors (QWIPs) have been used to detect infrared radiations through the principle based on the localized stated in quantum wells (QWs) [1]. The mature III-V compound semiconductor technology used to fabricate these devices results in much lower costs, larger array sizes, higher pixel operability, and better uniformity than those achievable with competing technologies such as HgCdTe. Especially, GaAs/AlGaAs QWIPs have been extensively used for large focal plane arrays (FPAs) of infrared imaging system. However, the research efforts for increasing sensitivity and operating temperature of the QWIPs still have pursued. The modification of heterostructures [2] and the various fabrications for preventing polarization selection rule [3] were suggested. In order to enhance optical performances of the QWIPs, double barrier quantum well (DBQW) structures will be introduced as the absorption layers for the suggested QWIPs. The DBWQ structure is an adequate solution for photodetectors working in the mid-wavelength infrared (MWIR) region and broadens the responsivity spectrum [4]. In this study, InGaAs/GaAs/AlGaAs double barrier quantum well infrared photodetectors (DB-QWIPs) are successfully fabricated and characterized. The heterostructures of the InGaAs/GaAs/AlGaAs DB-QWIPs are grown by molecular beam epitaxy (MBE) system. Photoluminescence (PL) spectroscopy is used to examine the heterostructures of the InGaAs/GaAs/AlGaAs DB-QWIP. The mesa-type DB-QWIPs (Area : $2mm{\times}2mm$) are fabricated by conventional optical lithography and wet etching process and Ni/Ge/Au ohmic contacts were evaporated onto the top and bottom layers. The dark current are measured at different temperatures and the temperature and applied bias dependence of the intersubband photocurrents are studied by using Fourier transform infrared spectrometer (FTIR) system equipped with cryostat. The photovoltaic behavior of the DB-QWIPs can be observed up to 120 K due to the generated built-in electric field caused from the asymmetric heterostructures of the DB-QWIPs. The fabricated DB-QWIPs exhibit spectral photoresponses at wavelengths range from 3 to $7{\mu}m$. Grating structure formed on the window surface of the DB-QWIP will induce the enhancement of optical responses.

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