• International Journal of Fuzzy Logic and Intelligent Systems
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• v.2 no.1
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• pp.33-37
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• 2002

Insulation aging diagnosis system provides early warning regarding electrical equipment defects. Early warning is very important in that it can avoid great losses resulting from unexpected shutdown of the production line. Since relations of insulation aging and partial discharge dynamics are non-linear. it is very difficult to provide early warning in an electrical equipment. In this paper, we propose the design method of insulation aging diagnosis system that use a electromagnetic wave and acoustic signal to diagnose an electrical equipment. Proposed system measures the partial discharge on-line from DAS(Data Acquisition System and acquires 2D patterns from analyzing it. For filtering the noise contained in sensor signals we used ICA algorithms. Using this data, we design of the neuro-fuzzy model that diagnoses an electrical equipment and is investigated in this paper. Validity of the new method is asserted by numerical simulation.

• Journal of the Korean Operations Research and Management Science Society
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• v.18 no.3
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• pp.151-157
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• 1993

In this paper, we investigate the effects of yield randomness for lot-sizing in a multi-stage production system. The practical importance of incorporating yield randomness into production models has been emphasized by many researchers. Yield randomness, especially in semiconductor manufacturing, poses a mojor challenge for production planning and control. The task becomes even more difficult if the demand for final product is uncertain. An attempt to meet the demand with a higher level of confidence forces one to release more input in the fabrication line. This leads to excessive work-in-process (WIP) inventories which cause jobs to spend unpredictably longer time waiting for the machines. The result is that it is more difficult to meet demand with exceptionally long cycle time and puts further pressure to increase the safety stocks. Due to this spiral effect, it is common to find that the capital tied in inventory is the msot significant factor undermining profitability. We propose a policy to determine the quantity to be processed at each stage of a multi-stage production system in which the yield at each stage may be random and may need rework.

• Laser Solutions
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• v.14 no.1
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• pp.14-18
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• 2011

Semiconductor industry demands decrease in line/space dimensions of IC substrates. Particularly for IC substrates for CPU, line/space dimensions below $10{\mu}m/10{\mu}m$ are expected to be used in production since 2014. Conventional production technologies (SAP, etc.) based on photolithography are widely agreed to be reaching capability limits. To address this limitation, the embedded circuit fabrication technology using laser ablation has been recently developed. In this paper, we used a nanosecond UV laser and a picosecond UV laser to fabricate embedded circuit patterns into a buildup film with $SiO_2$ powders for IC substrate. We conducted SEM and EDS analysis to investigate surface quality of the embedded circuit patterns. Experimental results showed that due to higher recoil pressure, picosecond UV laser ablation of the buildup film generated a better surface roughness.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.39 no.3
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• pp.147-155
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• 2016

Industry 4.0's goal is the 'Smart Factory' that integrates and controls production process, procurement, distribution and service based on the fundamental technology such as internet of the things, cyber physical system, sensor, etc. Basic requirement for successful promotion of this Industry 4.0 is the large supply of semiconductor. However, company I who produces dicing blades has difficulty to meet the increasing demand and has hard time to increase revenue because its raw material includes high price diamond, and requires very complex and sensitive process for production. Therefore, this study is focused on understanding the problems and presenting optimal plan to increase productivity of dicing blade manufacturing processes. We carried out a study as follows to accomplish the above purposes. First, previous researches were investigated. Second, the bottlenecks in manufacturing processes were identified using simulation tool (Arena 14.3). Third, we calculate investment amount according to added equipments purchase and perform economic analysis according to cost and sales increase. Finally, we derive optimum plan for productivity improvement and analyze its expected effect. To summarize these results as follows : First, daily average blade production volume can be increased two times from 60 ea. to 120 ea. by performing mixing job in the day before. Second, work flow can be smoother due to reduced waiting time if more machines are added to improve setting process. It was found that average waiting time of 23 minutes can be reduced to around 9 minutes from current process. Third, it was found through simulation that the whole processing line can compose smoother production line by performing mixing process in advance, and add setting and sintering machines. In the course of this study, it was found that adding more machines to reduce waiting time is not the best alternative.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.70-82
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• 2014

A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in $0.18{\mu}m$ standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is $17.6ppm/^{\circ}C$, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately $0.03mm^2$.

• Industrial Engineering and Management Systems
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• v.4 no.1
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• pp.54-67
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• 2005

This paper provides an evaluation of an optimization-based, multiple-input double-output (MIDO) run-to-run (R2R) control scheme for general semiconductor manufacturing processes. The controller in this research, termed adaptive dual response optimizing controller (ADROC), can serve as a process optimizer as well as a recipe regulator between consecutive runs of wafer fabrication. In evaluation, it is assumed that the equipment model could be appropriately described by a pair of second-order polynomial functions in terms of a set of controllable variables. Of practical relevance is to consider a drifting effect in the equipment model since in common semiconductor practice the process tends to drift due to machine aging and tool wearing. We select a typical application of R2R control to chemical mechanical planarization (CMP) in semiconductor manufacturing in this evaluation, and there are five different CMP process scenarios demonstrated, including mean shift, variance increase, and IMA disturbances. For the controller, ADROC, an on-line estimation technique is implemented in a self-tuning (ST) control manner for the adaptation purpose. Subsequently, an ad hoc global optimization algorithm based on the dual response approach, arising from the response surface methodology (RSM) literature, is used to seek the optimum recipe within the acceptability region for the execution of next run. The main components of ADROC are described and its control performance is assessed. It reveals from the evaluation that ADROC can provide excellent control actions for the MIDO R2R situations even though the process exhibits complicated, nonlinear interaction effects between control variables, and the drifting disturbances.

• Journal of the Semiconductor & Display Technology
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• v.20 no.1
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• pp.25-31
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• 2021

The semiconductor and display equipment demands an ultra-fine precision of several nm to several ㎛, and the scale is getting smaller due to the explosive development. The manufacturing process equipment for such products with ultra-fine precision is very sensitive to ultra-small vibrations flowing from the floor, resulting in problems of production defects and yield degradation. The vibration criteria are a standard that regulates the vibration environment of the floor where such precision process equipment will be installed. The BBN vibration criteria defined the allowable vibration velocity level in the frequency domain with a flat and inclined line and presented a rating according to it. However, the actual vibration criteria have appeared with various magnitudes in the frequency domain according to the dynamic characteristics of individual equipment. In this study, the relationship between the relative motion of two major points in the equipment and the vibration magnitude of the floor is presented using the frequency response function of a simple 3-DOF model. It is describing the magnitudes according to the frequency of the floor vibration that guarantees the allowable relative motion and this can be used as the vibration criteria. In order to obtain the vibration criteria experimentally a method of extracting through a modal test was introduced and verified analytically. It provides vulnerable frequency and magnitude to floor vibration in consideration of the dynamic characteristics of individual equipment. And it is possible to know necessary to improve the dynamic characteristics of the equipment, and it can be used to check the vibration compatibility of the place where the equipment will be installed.

• Journal of the Semiconductor & Display Technology
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• v.9 no.4
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• pp.13-18
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• 2010

Extreme ultraviolet (EUV) lithography using 13.5 nm wavelengths is expected to be adopted as a mass production technology for 32 nm half pitch and below. One of the new issues introduced by EUV lithography is the shadowing effect. Mask shadowing is a unique phenomenon caused by using mirror-based mask with an oblique incident angle of light. This results in a horizontal-vertical (H-V) biasing effect and ellipticity in the contact hole pattern. To minimize the shadowing effect, a refilled mask is an available option. The concept of refilled mask structure can be implemented by partial etching into the multilayer and then refilling the trench with an absorber material. The simulations were carried out to confirm the possibility of application of refilled mask in 32 nm line-and-space pattern under the condition of preproduction tool. The effect of sidewall angle in refilled mask is evaluated on image contrast and critical dimension (CD) on the wafer. We also simulated the effect of refilled absorber thickness on aerial image, H-V CD bias, and overlapping process window. Finally, we concluded that the refilled absorber thickness for minimizing shadowing effect should be thinner than etched depth.

• Journal of the Semiconductor & Display Technology
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• v.7 no.2
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• pp.23-27
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• 2008

Recently, regulation for THD (Total Harmonic Distortion) such as IEC 61000-3-2, IEEE 519 is being reinforced about a product which directly connects to AC line in order to prevent distortion of common power source in electronic equipment and electrical machinery. In order to satisfy these regulations, conventional circuits were used two-stage structure attached power factor correction circuit at ahead of converter but this method complicate the circuit and then a number of element increases thereupon the cost of production rises. in this paper, we propose a high efficiency single-stage 300W PFC fly-back converter that improved power factor and efficiency than conventional two-stage power module.

• Journal of Radiation Industry
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• v.8 no.3
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• pp.141-146
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• 2014

Nickel (Ni) electroplating was implemented by using a metal Ni powder in order to establish a $^{63}Ni$ plating condition on the PN junction semiconductor needed for production of beta-voltaic battery. PN junction semiconductors with a Ni seed layer of 500 and $1000{\AA}$ were coated with Ni at current density from 10 to $50mA\;cm^{-2}$. The surface roughness and average grain size of Ni deposits were investigated by XRD and SEM techniques. The roughness of Ni deposit was increased as the current density was increased, and decreased as the thickness of Ni seed layer was increased. The results showed that the optimum surface shape was obtained at a current density of $10mA\;cm^{-2}$ in seed layer with thickness of $500{\AA}$, $20mA\;cm^{-2}$ of $1000{\AA}$. Also, pure Ni deposit was well coated on a PN junction semiconductor without any oxide forms. Using the line width of (111) in XRD peak, the average grain size of the Ni thick firm was measured. The results showed that the average grain size was increased as the thickness of seed layer was increased.