• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.20-23
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing(CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical polishing(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commercial slurries pads, and post-CMP cleaning alternatives are discuss, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper deposition is a mature process from a historical point of view, but a very young process from a CMP perspective. While copper electro deposition has been used and studied for decades, its application to Cu damascene wafer processing is only now gaining complete acceptance in the semiconductor industry. The polishing mechanism of Cu-CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper passivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.70-71
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• 2005

The electrical performances of organic thin-film transistors (OTFTs) have been improved for the last decade. In this paper, it was demonstrated that the electrical characteristics of the organic thin film transistors (OTFTs) were improved by using polymeric material as adhesion layer on gate insulator. We have investigated OTFTs with polyimide adhesion layer which was fabricated by vapor deposition polymerization (VDP) processing and formed by co-deposition of 6FDA and ODA. It was found that the OTFTs with adhesion layer showed better electrical characteristics than with bare layer because of good matching between semiconductor and gate insulator. Our devices of performance are field effect mobility of $0.4cm^2$/Vs, threshold voltage of -0.8 V and on-of current ratio of $10^6$. In addition, to improve the electrical characteristics of OTFT, we have reduced the thickness of adhesion layer up to a few nanometrs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.61-62
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• 2006

In this paper, it was demonstrated that organic thin- film transistors (OTFTs) were fabricated with the organic adhesion layer between an organic semiconductor and a gate insulator by vapor deposition polymerization (VDP) processing. In order to form polymeric film as an adhesion layer, VDP process was also introduced instead of spin-coating process, where polymeric film was co-deposited by high-vacuum thermal evaporation from 6FDA and ODA followed by curing. The saturated slop in the saturation region and the subthreshold nonlinearity in the triode region were c1early observed in the electrical output characteristics in our organic thin film transistors using the staggered-inverted top-contact structure. Field effect mobility, threshold voltage, and on-off current ratio in 15-nm-thick organic adhesion layer were about $0.5\;cm^2/Vs$, -1 V, and $10^6$, respectively. We also demonstrated that threshold voltage depends strongly on the delay time when a gate voltage has been applied to bias stress.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.563-564
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• 2006

Recently, CMP (Chemical Mechanical Polishing) is one of very important processing in semiconductor technology because of large integration and application of design role. CMP is a planarization process of wafer surface using the chemical and mechanical reactions. One of the most important components of the CMP system is the polishing pad. During the CMP process, the pad itself becomes smoother and glazing. Therefore it is necessary to have a pad conditioning process to refresh the pad surface, to remove slurry debris and to supply the fresh slurry on the surface. A diamond disk use during the pad conditioning. There are diamonds on the surface of diamond disk to remove slurry debris and to polish pad surface slightly, so density, shape and size of diamond are very important factors. In. this study, we characterized diamond disk with 9 kinds of sample.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.10
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• pp.864-869
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• 2009

The measurement of contact wire uplift in electric railways is one of the most important test parameters to accepting the maximum permitted speed of new electric vehicles and pantographs. The contact wire uplift can be measured over short periods when the pantograph passes monitoring stations. In this paper, a high-speed image measurement system and its image processing method are being developed to evaluate dynamic uplift of overhead contact wires caused by pantograph contact forces of Korea Tilting Train eXpress (TTX) and Korea Train eXpress (KTX). The image measurement system was implemented utilizing a high-speed CMOS (Complementary Metal Oxide Semiconductor) camera and gigabit ethernet LAN. Unlike previous systems, the uplift measurement system using high speed camera is installed on the side of the rail, making maintenance convenient. On-field verification of the uplift measurement system for overhead contact wire using high speed camera was conducted by measuring uplift of the TTX followed by operation speeds at the Honam conventional line and high-speed railway line. The proposed high-speed image measurement system to evaluate dynamic uplift of overhead contact wires shows promising on-field applications for high speed trains such as KTX and TTX.

• Journal of the Korea Society for Simulation
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• v.24 no.3
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• pp.17-26
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• 2015

A cluster tool used in many kinds of semiconductor processes for improving the performance and the quality of wafers has a simple configuration, but its schedule is not easy because of its parallel processing module, a lack of intermediate buffers, and time constraints. While there have been many studies on its schedule, most of them have focused on full cycles in which identical work cycles are repeated under constant task times. In this research, we suggest strategies of start-up transient scheduling which satisfies time constraints and converges into a desirable steady schedule for full work cycle. The proposed schedules are expected robust under the stationary stochastic task times. Finally, we show that the strategies make schedules enters the desirable steady schedule and robust using the simulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.3
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• pp.187-191
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• 2019

Advances in laser technology have enabled ultra-high-speed ultra-precise processing, thus expanding potential applications to the semiconductor, medical, and photovoltaic industries. In particular, laser scribing technology has been applied to the production of shingled solar modules. In this work, we analyze the effect of laser scribing conditions, e.g., scribing depth, on the characteristics of the resulting divided solar cells. When the scribing depth was greater than $100{\mu}m$, the solar cells were well separated. In addition, the desired scribing depths were reached in fewer scans when the laser spot overlap was 100%. The efficiency of the divided cells decreased due to the high series resistance at scribing depths of less than $100{\mu}m$. However, at scribing depths of approximately $100{\mu}m$, the series resistance was low and efficiency reduction was minimized.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.3
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• pp.264-268
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• 2022

High pressure deuterium (HPD) annealing is an advancing technology for the fabrication of modern semiconductor devices. In this work, gate-enclosed FETs are fabricated on a silicon substrate as test vehicles. After a cycle for the HPD annealing, the device parameters such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), off-state current (I_OFF), and gate leakage (I_G) were measured and compared depending on the HPD. The HPD annealing can passivate the dangling bonds at Si-SiO₂ interfaces as well as eliminate the bulk trap in SiO₂. It can be concluded that adding the HPD annealing as a fabrication process is very effective in improving device reliability, performance, and variability.

• Transactions of Materials Processing
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• v.31 no.5
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• pp.290-295
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• 2022

Recently, the use of high-tech ceramic parts in functional electronic parts, automobile parts and semiconductor equipment parts is increasing. These ceramics materials are required to have high reproducibility, reliability, large size and complex shapes. The researchers initiated the work to develop a new shaping method called gel casting, which allows high performance ceramic materials with a complex shape to be produced. The manufacturing process parameters of gel casting include uniform mixing of the initiator, bubble removal, and slip injection. In this study, we analyzed the dispersion and gelation characteristics according to the change in the additive content of the alumina slurry in the gel casting process. The alumina slurry for gel casting was prepared by mixing a solvent, a monomer and a dispersant through a ball mill. Alumina powder and a gelation initiator were added to the mixed solution, and ball milling was performed for 24 hours. A viscosity of 6,435 cps and a stable zeta potential value were obtained under the conditions of alumina powder content of 55 vol% and dispersant 2.0 wt%. After curing for 12 hours by adding aps 0.1wt%, TEMED 0.2wt%, and Monomer 3, 5wt%, it was possible to separate from the molding cup, confirming that the gelation was completed.

• Tribology and Lubricants
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• v.38 no.4
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• pp.152-161
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• 2022

Chemical mechanical planarization (CMP) is a technology that planarizes the surfaces of semiconductor devices using chemical reaction and mechanical material removal, and it is an essential process in manufacturing highly integrated semiconductors. In the CMP process, a conditioning process using a diamond conditioner is applied to remove by-products generated during processing and ensure the surface roughness of the CMP pad. In previous studies, prediction of pad wear by CMP conditioning has depended on numerical analysis studies based on mathematical simulation. In this study, using an artificial neural network, the ratio of conditioner coverage to the distance between centers in the conditioning system is input, and the average conditioning density, standard deviation, nonuniformity (NU), and conditioning density distribution are trained as targets. The result of training seems to predict the target data well, although the average conditioning density, standard deviation, and NU in the contact area of wafer and pad and all areas of the pad have some errors. In addition, in the case of NU, the prediction calculated from the training results of the average conditioning density and standard deviation can reduce the error of training compared with the results predicted through training. The results of training on the conditioning density profile generally follow the target data well, confirming that the shape of the conditioning density profile can be predicted.