• Journal of Surface Science and Engineering
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• v.41 no.1
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• pp.38-42
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• 2008

316L stainless steel welding tube was electrolytically polished and the inner surface characteristics of the tube were tested. Electro-polishing variables such as current, voltage, concentration of electrolyte and electropolishing time were changed to seek for optimum condition. These makes a optimum conditions for the electro-polishing as 4000 A, 9 V, 1.7 specific gravity of electrolyte, and 30 minute of electro-polishing time. It makes the surface roughness as Ra < $0.25{\mu}m$. XPS test resulted as the ratio of CrO/FeO equals or more to 3/1. AES test resulted as the thickness of CrO film of $38{\AA}$. DTA test resulted as the tube did not react with $N_2,\;H_2\;and\;O_2$ gas below 1073K. As summarize above results, the electro- polished 316L stainless steel welding tube satisfied the conditions to apply as a pipeline for semi- conductor production facility and clean room.

• ETRI Journal
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• v.19 no.3
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.510-513
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• 2003

Our Zn diffusion into n-type $GaAs_{0.40}P_{0.60}$ used ampoule-tube method to increase IV. N-type epitaxial wafers were preferred by $H_2SO_4$-based pre-treatment. $SiO_2$ thin film was deposited by PECVD for some wafers. Diffusion times and diffusion temperatures respectability are 1, 2, 3 hr and 775, $805^{\circ}C$. LED chips were fabricated by the diffused wafers at Fab. The peak wavelength of all chips showed about $625{\sim}650\;nm$ and red color. The highest IV is about 270 mcd at the diffusion condition of $775^{\circ}C$, 3h for the wafers which didn't deposit $SiO_2$ thin films. Also, the longer diffusion time is the higher IV for the wafers which deposit $SiO_2$ thin films.

• Fire Science and Engineering
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• v.26 no.5
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• pp.41-47
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• 2012

As a core process in the manufacture of state-of-the-art industrial technologies such as semiconductor and LCD, a clean room is the most important process which can affect the performance and quality of products drastically. Nevertheless, scientific research on comprehensive safety measures from a fire protection standpoint is not being carried out in Korea. This study aims to derive measures to improve smoke control systems by identifying performance and problems of smoke systems installed in clean rooms as an LCD manufacturing process and analyzing fire and evacuation simulations considering several scenarios. As a result of analysis of fires and smoke in a clean roomas an LCD manufacturing process, it is found to be necessary to stop air handling units through interlocking in case of a fire and exhaust smoke out of the room through the top of FAB in consideration of buoyancy of smoke. It is also found to be necessary to install quick response sprinkler heads and accessories to accelerate the response time, because the heat-accumulating performance of sprinkler heads decreases in this application. Despite its low density of dwelling due to the automation process, clean room is characterized by an array of complex production equipment and working environment requiring dustproof clothes, which makes it difficult to acquire evacuation safety performance. Thus, thorough control of danger factors in processes and periodic education and training are required. It is also necessary to establish a level of domestic technologies equivalent to the level of standards of advanced countries in fire protection.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.8
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• pp.180-186
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• 2002

Hot Plate is the major unit that it used to remove damp of wafer surface, to strength adhesion of photoresist (PR) and to bake coated PR in FAB process of semiconductor. The badness of Hot Plate (HP) has directly influence upon the performance of wafer, it is necessary to guarantee the performance of HP. In this study, a reliability evaluation system has been designed and developed, which is to measure and to estimate thermal uniformity and flatness of HP in range of temperature 0~$250^\circC$. This system has included the techniques which measures and analyzes thermal uniformity using infrared thermal vision, and which compensates measuring error of flatness using laser displacement sensor For measuring flatness, a measurement stage of 3 axes are developed which adapts the precision encoder. The allowable error of this system in respect of thermal uniformity is less $than\pm0.1^\circC$ and in respect of flatness is less $than\pm$1mm . It is expected that the developed system can measure from $\Phi200mm\;(wafer 8＂)\;to\;\Phi300mm$ (wafer 12＂) and also can be used in performance test of the Cool Plate and industrial heater, etc.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.699-701
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• 2011

The Next-generation IT technology has been evolving from single technique to another which has merged, converging characteristics. The government categorized the 5 essential technologies to secure competitiveness in designing system semiconductors as smart motor vehicle info-tainment platform, smart TV multimedia system, smart phone analog interface technique, smart convergence digital communication and RF techniques, and advanced power management for smart devices. Also, it designated smart phone, smart TV, smart motor vehicle, and smart pad as the key industries. Such core techniques will become the key technologies of semiconductor design to secure the competitiveness of the next generation smart devices and the techniques can be transferred to fab-less design companies. In this contribution, we analyze the issues and the problems of the SoC design trends for smart motor vehicle info-tainment platforms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.668-670
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• 2011

The Next-generation IT technology has been evolving from single technique to another which has merged, converging characteristics. The government categorized the 5 essential technologies to secure competitiveness in designing system semiconductors as smart motor vehicle info-tainment platform, smart TV multimedia system, smart phone analog interface technique, smart convergence digital communication and RF techniques, and advanced power management for smart devices. Also, it designated smart phone, smart TV, smart motor vehicle, and smart pad as the key industries. Such core techniques will become the key technologies of semiconductor design to secure the competitiveness of the next generation smart devices and the techniques can be transferred to fab-less design companies. In this contribution, we analyze the issues and the problems of the smart phone analog and interface techniques.

• Asia-Pacific Journal of Business Venturing and Entrepreneurship
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• v.9 no.2
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• pp.87-95
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• 2014

The High-price development & testing tools and IP infratstructures are required for the development of system semi-conductors, but SMEs have not ability to prepare for them. Recently in terms of the miniaturization and the advancement of semiconductor process, the cost of the semi-conductor development have shown the rising tendency and the market-based design tools used are requied to be upgraded due to the advancement in the environment and technology. On the contray, many other contries such as Taiwan, Japan, China, and User are supporting this system semi-conductor industry. Korean government is trying to build the research infrastructure for system semi-conductor industry that aims to reduce the costs of the design infrastructure investment, to support the companies of system semi-conductor development and to incubate the fab-less start-ups. This study analyzes the feasibility of the project, by using the AHP analysis and the results shows that this project is considered feasible because the AHP overall score is evaluated as 0.840, the overall score is greater than or equal to 0.55.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.79-90
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• 2000

In this paper, a high-performance floating point unit, which is suitable for high-performance superscalar microprocessors and supports IEEE 754 standard, is designed. Floating-point arithmetic unit (AU) supports all denormalized number processing through hardware, while eliminating the additional delay time due to the denormalized number processing by proposing the proposed gradual underflow prediction (GUP) scheme. Contrary to the existing fixed-radix implementations, floating-point divide/square root unit adopts a new architecture which determines variable length quotient bits per cycle. The new architecture is superior to the SRT implementations in terms of performance and design complexity. Moreover, sophisticated exception prediction scheme enables precise exception to be implemented with ease on various superscalar microprocessors, and removes the stall cycles in division. Designed floating-point AU and divide/square root unit are integrated with and instruction decoder, register file, memory model and multiplier to form a floating-point unit, and its function and performance is verified.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.145-148
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• 2003

Recently, the recycle of CMP (chemical mechanical polishing) slurries have been positively considered in order to reduce the high COO (cost of ownership) and COC (cost of consumables) in CMP process. Among the composition of slurries (buffer solution, bulk solution, abrasive particle, oxidizer, inhibitor, suspension, antifoaming agent, dispersion agent), the abrasive particles are one of the most important components. Especially, the abrasive particles of slurry are needed in order to achieve a good removal rate. However, the cost of abrasives, is still very high. In this paper, we have collected the silica abrasive powders by filtering after subsequent CMP process for the purpose of abrasive particle recycling. And then, we have studied the possibility of recycle of reused silica abrasive through the analysis of particle size and hardness. Also, we annealed the collected abrasive powders to promote the mechanical strength of reduced abrasion force. Finally, we compared the CMP characteristics between self-developed KOH-based silica abrasive slurry and original slury, As our experimental results, we obtained the comparable removal rate and good planarity with commercial products. Consequently, we can expect the saving of high cost slurry.