• Journal of Semiconductor Engineering
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• v.3 no.1
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• pp.154-160
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• 2022

In this paper, we design a DC-DC boost converter with RF noise immunity to supply a stable positive output voltage for OLED displays. For RF noise immunity, an input voltage variation reduction circuit (IVVRC) is adopted to ensure display quality by reducing the undershoot and overshoot of output voltage. The boost converter for a positive voltage Vpos operates in the SPWM-PWM dual mode and has a dead-time controller using a dead-time detector, resulting in increased power efficiency. A chip was fabricated using a 0.18 um BCDMOS process. Measurement results show that power efficiency is 30% ~ 76% for load current range from 1 mA to 100 mA. The boost converter with the IVVRC has an overshoot of 6 mV and undershoot of 4 mV compared to a boost converter without that circuit with 18 mV and 20 mV, respectively.

• Journal of the Korean Vacuum Society
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• v.4 no.S2
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• pp.90-94
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• 1995

Defects introduced by Si, Ge preamorphization and their effects on the dopant diffusion and electrical characteristics. Good crystalline quality are obtained after the annealing of Ge ion double implanted samples. The defect clusters under the a/c interface are expected to extend up to the deep in the Si ion implanted samples. The dislocation loops near the junction absorb the interstitial Si atoms resolving from the defect cluster and result in the prevention of enhanced boron diffusion near the tail region of boron profile and show good reverse current charactristics.

• Journal of the Korea Safety Management & Science
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• v.15 no.4
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• pp.253-260
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• 2013

The importance of environmental protection has been increased recently. Thus the environmental management was settled in an important global competition factor. In the meantime logistics cost occupied the 8.03% of sales at 2011. This portion was greater than the portion of other countries and it was needed the reduction of logistics cost to secure the competition power. As thus in this paper we prepared the process which diminish the environmental discharge and decrease the logistics cost. We proposed the process to apply the MFCA to SCM, until now the MFCA had been used generally in manufacturing process. We defined the loss in SCM and the plus logistic, minus logistic, logistic center and the classification of cost to adopt the MFCA to SCM.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.114.2-114.2
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• 2011

비정질 실리콘 박막 태양전지연구에 일반적으로 사용되고 있는 ASA (Advanced Semicon ductor Analysis) simulation을 이용하여 TCO/p에 삽입될 버퍼층의 최적 구조를 설계해보았다. 기본적인 p,i,n층 단일막 data 값을 고정시켜 버퍼층의 광학적 밴드갭을 1.75~1.95eV, 활성화 에너지를 0.3~0.4eV, 두께를 5~15nm로 가변해 보았다. 첫 번째로 동일한 활성화 에너지를 갖는 버퍼층의 광학적 밴드갭을 증가 시켰을 경우 built-in potential이 증가하였으며 이는 개방전압의 증가로 이어졌다. 두 번째로 활성화 에너지가 작은 경우 큰 경우에 비하여 Conduction-band와 Fermi-level의 차이가 증가 하게 되어 활성화 에너지가 큰 경우에 비해 높은 built-in potential을 얻을 수 있었다. 또한 버퍼층과 p층의 접합부분에서의 barrier가 활성화 에너지의 차이를 줄일수록 감소 함 을 알 수 있었다. 장벽의 감소로 정공의 흐름을 방해하는 요소가 줄어들었고 효율도 증가하였다. 마지막으로 버퍼층 두께가 두꺼워 질수록 박막 내에서 빛 흡수가 많아지게 되어 광 흡수층으로 가야할 빛의 양이 줄어들게 되어 단락전류값이 감소하는 것을 알 수 있었다. Simulation결과 버퍼층의 광학적 밴드갭이 1.95eV로 크고 활성화 에너지가 0.3eV이하로 p층에 비하여 낮으며 두께가 5nm로 얇을수록 좋다는 결과를 알 수 있었다.

• Transactions of Materials Processing
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• v.7 no.6
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• pp.554-561
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• 1998

This paper describes a research work of developing a computer-aided design of lead frame semicon-ductor with piercing operation which is very precise for progressive working. An approach to the sys-tem is based on to knowledge-based rules. Knowledge for the system is formulated from plasticity theories experimental results and the empirical knowledge of field experts. This system has been writ-ten using AutoLISP to AutoCAD on a personal computer and is composed of three main modules which are input and shape treatment production feasibility check and strip-layout module. Based on the knowledge-based rules the system is designed by considering several factors such as material and thickness of product complexities of blank geometry and punch profile, and availability of press. Also strip-layout drawing generated by piercing operation according to punch profiles considered V-notch dimple. pad chamfer spank cavity punch camber and cross bow of lead frame is displayed in graphic forms. This system can be used by a novice who may not have any knowledge of tool design and will invrease efficiencies to the designer in this field.

• Journal of Sensor Science and Technology
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• v.4 no.4
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• pp.23-28
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• 1995

The ISFET glucose and sucrose sensors containing platinum electrode and photopolymeric enzyme membrane were fabricated. The platinum working electrode was used for the electrolysis of hydrogen peroxide, which was the other product of the enzyme reaction, to improve sensing characteristics of the sensors. In order to improve response time, photo-crosslinkable polymer(PVA-SbQ) was used to the matrix for the enzyme immobilized membrane. The characteristics of glucose and sucrose sensors were investigated according to the variation of platinum electrode area. The response time was about $3{\sim}5$ minutes and determinations of glucose and sucrose in the range of about $30{\sim}300mg/dl$ could be possible.

• Transactions of Materials Processing
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• v.7 no.2
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• pp.168-176
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• 1998

Hot workability of the AA5083 alloy ws investigated by torsion test at temperature ranges of $350{\sim}520^{\circ}C$ and strain rates of 0.5, 1.0, and 3.0/sec. The flow stress and hot ductility of the AA5083 alloy as a function of deformation variables such as temperature and train rate were studied. The microstructural evolution of the AA5083 alloy was studied in relation to Zener-Hollomon parameter (Z=exp( /RT) Also the hot restoration mechanism of the AA5083 alloy was small when Z val-ues were higher than $1.73{\times}1016/sec(370^{\circ}C,\;0.5/sec)$ In addition the difference microstructures during hot deformation. It was found that the increase of flow curves and deformed microstructures during hot deformation. It was found that the increase of flow stress of the AA5083 alloy was small when Z val-ues were higher than $1.73{\times}1016/sec(370^{\circ}C.\;0.5/sec)$. However under the low Z values less than $1.73{\times}1016/sec(370^{\circ}C,\;0.5/sec)$ the flow stress increase with increasing the Z values. The large dispersoid particles in the matrix grain decreased the flow strain of the AA5083 alloy because it caused the stress concentration during hot deformation.

• Membrane Journal
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• v.9 no.3
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• pp.185-192
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• 1999

The ultrafiltration characteristics of wafer processing wastewater produced from semicon¬ductor industry was investigated for wastewater reuse. Using the pilot-scale ultrafiltration system con¬taining poly sulfone hollow fiber membranes (MWCO : 10,000, 20,000, 30,(00), the membrane performance, such as flux, rejection rate and concentration factor for flux was examined. The SDhs, turbidity, electrical conductivity and concentration of Si particles were measured, and the possibility of permeate reuse was validated from the experimental results. It was shown that the flux was recovered by the sweeping with air and water effectively. The permeate flux of 30,000 MWCO membrane was about 5 times higher than that of 10,000 and 20,000 MWCO membranes. The concentration of Si particle in the saw wastewater was analyzed 3.8-5.6 mg/$\ell$ and that of Si particle in the permeate was analyzed less than 0.2${\mu}g$/$\ell$. This means the rejection of silicon particle was over 96%.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.1-13
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• 1999

As the complexity of DSP (Digital Signal Processing) applications increases, the need for new architectures supporting efficient high-level language compilers also grows. By combining several DSP processor specific features, such as single cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping, with a RISC core having many general purpose registers and orthogonal instructions, a high-performance and compiler-friendly RISC-based DSP processors can be designed. In this study, we develop a code-converter that can exploit these DSP architectural features by post-processing compiler-generated assembly code, and evaluate the performance effects of each feature using seven DSP-kernel benchmarks and a QCELP vocoder program. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.830-833
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• 2007

In this paper, we implemented a $17{\times}17b$ binary digital multiplier using radix-4 Booth;s algorithmand proposed an efficient testing methodology for the full-custom design. A two-stage pipeline architecture was applied to achieve higher throughput and 4:2 adders were used for regular layout structure in the Wallace tree partition. Several chips were fabricated using LG Semicon 0.6-um 3-Metal N-well CMOS technology. We did fault simulations efficiently using the proposed test method resulting in the reduction of the number of faulty nodes by 88%. The chip contains 9115 transistors and the core area occupies $1135^*1545$ mm2. The functional tests using ATS-2 tester showed that it can operate with 24 MHz clock at 5.0 V at room temperature.